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Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -908,6 +908,11 @@ def p_imm : Operand<i32> {
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let DecoderMethod = "DecodeCoprocessor";
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}
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def pf_imm : Operand<i32> {
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let PrintMethod = "printPImmediate";
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let ParserMatchClass = CoprocNumAsmOperand;
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}
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def CoprocRegAsmOperand : AsmOperandClass {
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let Name = "CoprocReg";
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let ParserMethod = "parseCoprocRegOperand";
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@ -4306,7 +4311,7 @@ def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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let Inst{23-20} = opc1;
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}
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def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
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c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
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NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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@ -321,3 +321,6 @@
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# CHECK: ldmgt sp!, {r9}
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0x00 0x02 0xbd 0xc8
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# CHECK: cdp2 p10, #0, c6, c12, c0, #7
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0xe0 0x6a 0x0c 0xfe
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@ -594,6 +594,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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IMM("jtblock_operand");
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IMM("nohash_imm");
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IMM("p_imm");
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IMM("pf_imm");
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IMM("c_imm");
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IMM("coproc_option_imm");
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IMM("imod_op");
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