From e5544f851a2a3f7b06339b132e60ad2f2d53e7b8 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Thu, 20 Jan 2005 20:29:23 +0000
Subject: [PATCH] Simplify the shift-expansion code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19721 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 8bb88a7c3f1..6992b403a6b 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1237,13 +1237,16 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
   SDOperand InL, InH;
   ExpandOp(Op, InL, InH);
   SDOperand ShAmt = LegalizeOp(Amt);
-  SDOperand OShAmt = ShAmt;  // Unmasked shift amount.
   MVT::ValueType ShTy = ShAmt.getValueType();
   
   unsigned NVTBits = MVT::getSizeInBits(NVT);
   SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy,           // NAmt = 32-ShAmt
                                DAG.getConstant(NVTBits, ShTy), ShAmt);
 
+  // Compare the unmasked shift amount against 32.
+  SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), ShAmt,
+                                DAG.getConstant(NVTBits, ShTy));
+
   if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
     ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt,             // ShAmt &= 31
                         DAG.getConstant(NVTBits-1, ShTy));
@@ -1255,10 +1258,8 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
     SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
                                DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
                                DAG.getNode(ISD::SRL, NVT, InL, NAmt));
-    SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt
+    SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
     
-    SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), OShAmt,
-                                  DAG.getConstant(NVTBits, ShTy));
     Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
     Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
   } else {
@@ -1266,17 +1267,15 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
                                DAG.getNode(ISD::SHL, NVT, InH, NAmt),
                                DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
     bool isSign = Opc == ISD::SRA;
-    SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt);
+    SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt);  // T2 = InH >> ShAmt&31
 
     SDOperand HiPart;
     if (isSign)
       HiPart = DAG.getNode(Opc, NVT, InH, DAG.getConstant(NVTBits-1, ShTy));
     else
       HiPart = DAG.getConstant(0, NVT);
-    SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), OShAmt,
-                                  DAG.getConstant(NVTBits, ShTy));
     Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
-    Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart,T2);
+    Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
   }
   return true;
 }