mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
Extract some methods from verifyLiveIntervals.
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161149 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
a62e1e8bc6
commit
e5c79a5c25
@ -212,6 +212,10 @@ namespace {
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void calcRegsRequired();
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void verifyLiveVariables();
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void verifyLiveIntervals();
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void verifyLiveInterval(const LiveInterval&);
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void verifyLiveIntervalValue(const LiveInterval&, VNInfo*);
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void verifyLiveIntervalSegment(const LiveInterval&,
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LiveInterval::const_iterator);
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};
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struct MachineVerifierPass : public MachineFunctionPass {
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@ -1138,281 +1142,291 @@ void MachineVerifier::verifyLiveIntervals() {
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const LiveInterval &LI = LiveInts->getInterval(Reg);
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assert(Reg == LI.reg && "Invalid reg to interval mapping");
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verifyLiveInterval(LI);
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}
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}
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for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
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I!=E; ++I) {
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VNInfo *VNI = *I;
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const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
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void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
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VNInfo *VNI) {
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if (VNI->isUnused())
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return;
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if (!DefVNI) {
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if (!VNI->isUnused()) {
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report("Valno not live at def and not marked unused", MF);
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*OS << "Valno #" << VNI->id << " in " << LI << '\n';
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}
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continue;
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}
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const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
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if (VNI->isUnused())
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continue;
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if (!DefVNI) {
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report("Valno not live at def and not marked unused", MF);
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*OS << "Valno #" << VNI->id << " in " << LI << '\n';
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return;
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}
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if (DefVNI != VNI) {
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report("Live range at def has different valno", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " where valno #" << DefVNI->id << " is live in " << LI << '\n';
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continue;
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}
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if (DefVNI != VNI) {
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report("Live range at def has different valno", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " where valno #" << DefVNI->id << " is live in " << LI << '\n';
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return;
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}
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
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if (!MBB) {
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report("Invalid definition index", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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continue;
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}
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
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if (!MBB) {
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report("Invalid definition index", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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return;
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}
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if (VNI->isPHIDef()) {
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if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
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report("PHIDef value is not defined at MBB start", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< ", not at the beginning of BB#" << MBB->getNumber()
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<< " in " << LI << '\n';
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}
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} else {
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// Non-PHI def.
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const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
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if (!MI) {
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report("No instruction at def index", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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continue;
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}
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bool hasDef = false;
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bool isEarlyClobber = false;
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for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
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if (!MOI->isReg() || !MOI->isDef())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
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if (MOI->getReg() != LI.reg)
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continue;
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} else {
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if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
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!TRI->regsOverlap(LI.reg, MOI->getReg()))
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continue;
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}
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hasDef = true;
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if (MOI->isEarlyClobber())
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isEarlyClobber = true;
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}
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if (!hasDef) {
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report("Defining instruction does not modify register", MI);
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*OS << "Valno #" << VNI->id << " in " << LI << '\n';
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}
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// Early clobber defs begin at USE slots, but other defs must begin at
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// DEF slots.
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if (isEarlyClobber) {
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if (!VNI->def.isEarlyClobber()) {
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report("Early clobber def must be at an early-clobber slot", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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}
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} else if (!VNI->def.isRegister()) {
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report("Non-PHI, non-early clobber def must be at a register slot",
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MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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}
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}
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if (VNI->isPHIDef()) {
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if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
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report("PHIDef value is not defined at MBB start", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< ", not at the beginning of BB#" << MBB->getNumber()
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<< " in " << LI << '\n';
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}
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return;
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}
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for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
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const VNInfo *VNI = I->valno;
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assert(VNI && "Live range has no valno");
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// Non-PHI def.
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const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
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if (!MI) {
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report("No instruction at def index", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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return;
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}
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if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
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report("Foreign valno in live range", MF);
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I->print(*OS);
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*OS << " has a valno not in " << LI << '\n';
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}
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if (VNI->isUnused()) {
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report("Live range valno is marked unused", MF);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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}
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
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if (!MBB) {
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report("Bad start of live segment, no basic block", MF);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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continue;
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}
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SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
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if (I->start != MBBStartIdx && I->start != VNI->def) {
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report("Live segment must begin at MBB entry or valno def", MBB);
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I->print(*OS);
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*OS << " in " << LI << '\n' << "Basic block starts at "
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<< MBBStartIdx << '\n';
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}
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const MachineBasicBlock *EndMBB =
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LiveInts->getMBBFromIndex(I->end.getPrevSlot());
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if (!EndMBB) {
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report("Bad end of live segment, no basic block", MF);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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continue;
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}
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// No more checks for live-out segments.
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if (I->end == LiveInts->getMBBEndIdx(EndMBB))
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continue;
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// The live segment is ending inside EndMBB
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const MachineInstr *MI =
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LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
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if (!MI) {
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report("Live segment doesn't end at a valid instruction", EndMBB);
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I->print(*OS);
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*OS << " in " << LI << '\n' << "Basic block starts at "
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<< MBBStartIdx << '\n';
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continue;
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}
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// The block slot must refer to a basic block boundary.
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if (I->end.isBlock()) {
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report("Live segment ends at B slot of an instruction", MI);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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}
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if (I->end.isDead()) {
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// Segment ends on the dead slot.
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// That means there must be a dead def.
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if (!SlotIndex::isSameInstr(I->start, I->end)) {
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report("Live segment ending at dead slot spans instructions", MI);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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}
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}
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// A live segment can only end at an early-clobber slot if it is being
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// redefined by an early-clobber def.
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if (I->end.isEarlyClobber()) {
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if (I+1 == E || (I+1)->start != I->end) {
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report("Live segment ending at early clobber slot must be "
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"redefined by an EC def in the same instruction", MI);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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}
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}
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// The following checks only apply to virtual registers. Physreg liveness
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// is too weird to check.
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if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
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// A live range can end with either a redefinition, a kill flag on a
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// use, or a dead flag on a def.
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bool hasRead = false;
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bool hasDeadDef = false;
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for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
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if (!MOI->isReg() || MOI->getReg() != LI.reg)
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continue;
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if (MOI->readsReg())
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hasRead = true;
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if (MOI->isDef() && MOI->isDead())
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hasDeadDef = true;
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}
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if (I->end.isDead()) {
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if (!hasDeadDef) {
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report("Instruction doesn't have a dead def operand", MI);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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}
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} else {
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if (!hasRead) {
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report("Instruction ending live range doesn't read the register",
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MI);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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}
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}
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}
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// Now check all the basic blocks in this live segment.
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MachineFunction::const_iterator MFI = MBB;
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// Is this live range the beginning of a non-PHIDef VN?
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if (I->start == VNI->def && !VNI->isPHIDef()) {
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// Not live-in to any blocks.
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if (MBB == EndMBB)
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continue;
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// Skip this block.
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++MFI;
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}
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for (;;) {
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assert(LiveInts->isLiveInToMBB(LI, MFI));
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// We don't know how to track physregs into a landing pad.
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if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
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MFI->isLandingPad()) {
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if (&*MFI == EndMBB)
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break;
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++MFI;
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continue;
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}
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// Is VNI a PHI-def in the current block?
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bool IsPHI = VNI->isPHIDef() &&
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VNI->def == LiveInts->getMBBStartIdx(MFI);
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// Check that VNI is live-out of all predecessors.
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for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
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PE = MFI->pred_end(); PI != PE; ++PI) {
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SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
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const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
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// All predecessors must have a live-out value.
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if (!PVNI) {
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report("Register not marked live out of predecessor", *PI);
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*OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
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<< '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
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<< PEnd << " in " << LI << '\n';
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continue;
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}
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// Only PHI-defs can take different predecessor values.
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if (!IsPHI && PVNI != VNI) {
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report("Different value live out of predecessor", *PI);
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*OS << "Valno #" << PVNI->id << " live out of BB#"
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<< (*PI)->getNumber() << '@' << PEnd
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<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
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<< '@' << LiveInts->getMBBStartIdx(MFI) << " in "
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<< PrintReg(Reg) << ": " << LI << '\n';
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}
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}
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if (&*MFI == EndMBB)
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break;
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++MFI;
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}
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}
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// Check the LI only has one connected component.
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bool hasDef = false;
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bool isEarlyClobber = false;
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for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
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if (!MOI->isReg() || !MOI->isDef())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
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ConnectedVNInfoEqClasses ConEQ(*LiveInts);
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unsigned NumComp = ConEQ.Classify(&LI);
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if (NumComp > 1) {
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report("Multiple connected components in live interval", MF);
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*OS << NumComp << " components in " << LI << '\n';
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for (unsigned comp = 0; comp != NumComp; ++comp) {
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*OS << comp << ": valnos";
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for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
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E = LI.vni_end(); I!=E; ++I)
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if (comp == ConEQ.getEqClass(*I))
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*OS << ' ' << (*I)->id;
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*OS << '\n';
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}
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if (MOI->getReg() != LI.reg)
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continue;
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} else {
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if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
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!TRI->regsOverlap(LI.reg, MOI->getReg()))
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continue;
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}
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hasDef = true;
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if (MOI->isEarlyClobber())
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isEarlyClobber = true;
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}
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if (!hasDef) {
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report("Defining instruction does not modify register", MI);
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*OS << "Valno #" << VNI->id << " in " << LI << '\n';
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}
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// Early clobber defs begin at USE slots, but other defs must begin at
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// DEF slots.
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if (isEarlyClobber) {
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if (!VNI->def.isEarlyClobber()) {
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report("Early clobber def must be at an early-clobber slot", MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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}
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} else if (!VNI->def.isRegister()) {
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report("Non-PHI, non-early clobber def must be at a register slot",
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MF);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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}
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}
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void
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MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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LiveInterval::const_iterator I) {
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const VNInfo *VNI = I->valno;
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assert(VNI && "Live range has no valno");
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if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
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report("Foreign valno in live range", MF);
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I->print(*OS);
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*OS << " has a valno not in " << LI << '\n';
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}
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if (VNI->isUnused()) {
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report("Live range valno is marked unused", MF);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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}
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
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if (!MBB) {
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report("Bad start of live segment, no basic block", MF);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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return;
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}
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SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
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if (I->start != MBBStartIdx && I->start != VNI->def) {
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report("Live segment must begin at MBB entry or valno def", MBB);
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I->print(*OS);
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*OS << " in " << LI << '\n'
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<< "Basic block starts at " << MBBStartIdx << '\n';
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}
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const MachineBasicBlock *EndMBB =
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LiveInts->getMBBFromIndex(I->end.getPrevSlot());
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if (!EndMBB) {
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report("Bad end of live segment, no basic block", MF);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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return;
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}
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// No more checks for live-out segments.
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if (I->end == LiveInts->getMBBEndIdx(EndMBB))
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return;
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// The live segment is ending inside EndMBB
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const MachineInstr *MI =
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LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
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if (!MI) {
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report("Live segment doesn't end at a valid instruction", EndMBB);
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I->print(*OS);
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*OS << " in " << LI << '\n'
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<< "Basic block starts at " << MBBStartIdx << '\n';
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return;
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}
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// The block slot must refer to a basic block boundary.
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if (I->end.isBlock()) {
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report("Live segment ends at B slot of an instruction", MI);
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I->print(*OS);
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*OS << " in " << LI << '\n';
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}
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if (I->end.isDead()) {
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// Segment ends on the dead slot.
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// That means there must be a dead def.
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if (!SlotIndex::isSameInstr(I->start, I->end)) {
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report("Live segment ending at dead slot spans instructions", MI);
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I->print(*OS);
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*OS << " in " << LI << '\n';
|
||||
}
|
||||
}
|
||||
|
||||
// A live segment can only end at an early-clobber slot if it is being
|
||||
// redefined by an early-clobber def.
|
||||
if (I->end.isEarlyClobber()) {
|
||||
if (I+1 == LI.end() || (I+1)->start != I->end) {
|
||||
report("Live segment ending at early clobber slot must be "
|
||||
"redefined by an EC def in the same instruction", MI);
|
||||
I->print(*OS);
|
||||
*OS << " in " << LI << '\n';
|
||||
}
|
||||
}
|
||||
|
||||
// The following checks only apply to virtual registers. Physreg liveness
|
||||
// is too weird to check.
|
||||
if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
|
||||
// A live range can end with either a redefinition, a kill flag on a
|
||||
// use, or a dead flag on a def.
|
||||
bool hasRead = false;
|
||||
bool hasDeadDef = false;
|
||||
for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
|
||||
if (!MOI->isReg() || MOI->getReg() != LI.reg)
|
||||
continue;
|
||||
if (MOI->readsReg())
|
||||
hasRead = true;
|
||||
if (MOI->isDef() && MOI->isDead())
|
||||
hasDeadDef = true;
|
||||
}
|
||||
|
||||
if (I->end.isDead()) {
|
||||
if (!hasDeadDef) {
|
||||
report("Instruction doesn't have a dead def operand", MI);
|
||||
I->print(*OS);
|
||||
*OS << " in " << LI << '\n';
|
||||
}
|
||||
} else {
|
||||
if (!hasRead) {
|
||||
report("Instruction ending live range doesn't read the register",
|
||||
MI);
|
||||
I->print(*OS);
|
||||
*OS << " in " << LI << '\n';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Now check all the basic blocks in this live segment.
|
||||
MachineFunction::const_iterator MFI = MBB;
|
||||
// Is this live range the beginning of a non-PHIDef VN?
|
||||
if (I->start == VNI->def && !VNI->isPHIDef()) {
|
||||
// Not live-in to any blocks.
|
||||
if (MBB == EndMBB)
|
||||
return;
|
||||
// Skip this block.
|
||||
++MFI;
|
||||
}
|
||||
for (;;) {
|
||||
assert(LiveInts->isLiveInToMBB(LI, MFI));
|
||||
// We don't know how to track physregs into a landing pad.
|
||||
if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
|
||||
MFI->isLandingPad()) {
|
||||
if (&*MFI == EndMBB)
|
||||
break;
|
||||
++MFI;
|
||||
continue;
|
||||
}
|
||||
|
||||
// Is VNI a PHI-def in the current block?
|
||||
bool IsPHI = VNI->isPHIDef() &&
|
||||
VNI->def == LiveInts->getMBBStartIdx(MFI);
|
||||
|
||||
// Check that VNI is live-out of all predecessors.
|
||||
for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
|
||||
PE = MFI->pred_end(); PI != PE; ++PI) {
|
||||
SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
|
||||
const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
|
||||
|
||||
// All predecessors must have a live-out value.
|
||||
if (!PVNI) {
|
||||
report("Register not marked live out of predecessor", *PI);
|
||||
*OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
|
||||
<< '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
|
||||
<< PEnd << " in " << LI << '\n';
|
||||
continue;
|
||||
}
|
||||
|
||||
// Only PHI-defs can take different predecessor values.
|
||||
if (!IsPHI && PVNI != VNI) {
|
||||
report("Different value live out of predecessor", *PI);
|
||||
*OS << "Valno #" << PVNI->id << " live out of BB#"
|
||||
<< (*PI)->getNumber() << '@' << PEnd
|
||||
<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
|
||||
<< '@' << LiveInts->getMBBStartIdx(MFI) << " in "
|
||||
<< PrintReg(LI.reg) << ": " << LI << '\n';
|
||||
}
|
||||
}
|
||||
if (&*MFI == EndMBB)
|
||||
break;
|
||||
++MFI;
|
||||
}
|
||||
}
|
||||
|
||||
void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
|
||||
for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
|
||||
I!=E; ++I)
|
||||
verifyLiveIntervalValue(LI, *I);
|
||||
|
||||
for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I)
|
||||
verifyLiveIntervalSegment(LI, I);
|
||||
|
||||
// Check the LI only has one connected component.
|
||||
if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
|
||||
ConnectedVNInfoEqClasses ConEQ(*LiveInts);
|
||||
unsigned NumComp = ConEQ.Classify(&LI);
|
||||
if (NumComp > 1) {
|
||||
report("Multiple connected components in live interval", MF);
|
||||
*OS << NumComp << " components in " << LI << '\n';
|
||||
for (unsigned comp = 0; comp != NumComp; ++comp) {
|
||||
*OS << comp << ": valnos";
|
||||
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
|
||||
E = LI.vni_end(); I!=E; ++I)
|
||||
if (comp == ConEQ.getEqClass(*I))
|
||||
*OS << ' ' << (*I)->id;
|
||||
*OS << '\n';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user