6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

Add some simplifications for MULH[SU]. This allows us to compile this:

Browse Source 
long %bar(long %X) {
  %Y = mul long %X, 4294967297
  ret long %Y
}

to this:

l1_bar:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, %EAX
        add %EDX, DWORD PTR [%ESP + 8]
        ret

instead of:

l1_bar:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EDX, 1
        mov %EAX, %ECX
        mul %EDX
        add %EDX, %ECX
        add %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %ECX
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22044 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-05-15 05:39:08 +00:00
parent 1e9448bce8
commit e5eb6f829c
1 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -843,6 +843,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
case ISD::XOR:
case ISD::UDIV:
case ISD::UREM:
case ISD::MULHU:
case ISD::MULHS:
assert(MVT::isInteger(VT) && "This operator does not apply to FP types!");
// fall through
case ISD::ADD:
@ -941,6 +943,16 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
}
break;
case ISD::MULHU:
case ISD::MULHS:
if (!C2) return N2; // mul X, 0 -> 0
if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0
return getConstant(0, VT);
// Many others could be handled here, including -1, powers of 2, etc.
break;
case ISD::UDIV:
// FIXME: Move this to the DAG combiner when it exists.
if ((C2 & C2-1) == 0 && C2) {