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R600/SI: Fix incorrect commute operation in shrink instructions pass

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We were commuting the instruction by still shrinking it using the
original opcode.

NOTE: This is a candidate for the 3.5 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214463 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2014-08-01 00:32:28 +00:00
parent 42deb12738
commit e5fc4208eb
4 changed files with 57 additions and 3 deletions
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11
lib/Target/R600/SIShrinkInstructions.cpp
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@@ -125,9 +125,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
Next = std::next(I);
MachineInstr &MI = *I;
int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
if (Op32 == -1)
if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
continue;
if (!canShrink(MI, TII, TRI, MRI)) {
@@ -138,6 +136,13 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
continue;
}
int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
// Op32 could be -1 here if we started with an instruction that had a
// a 32-bit encoding and then commuted it to an instruction that did not.
if (Op32 == -1)
continue;
if (TII->isVOPC(Op32)) {
unsigned DstReg = MI.getOperand(0).getReg();
if (TargetRegisterInfo::isVirtualRegister(DstReg)) {