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When expanding atomic load arith instructions, do not lose target flags. rdar://12453106

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165568 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-10-09 23:48:33 +00:00
parent c0dfffa448
commit e61e516a51
2 changed files with 63 additions and 44 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
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@ -12389,9 +12389,12 @@ X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
// Hi // Hi
MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX); MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX);
for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
if (i == X86::AddrDisp) if (i == X86::AddrDisp) {
MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32) MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
else // Don't forget to transfer the target flag.
MachineOperand &MO = MIB->getOperand(MIB->getNumOperands()-1);
MO.setTargetFlags(MI->getOperand(MemOpndSlot + i).getTargetFlags());
} else
MIB.addOperand(MI->getOperand(MemOpndSlot + i)); MIB.addOperand(MI->getOperand(MemOpndSlot + i));
} }
MIB.setMemRefs(MMOBegin, MMOEnd); MIB.setMemRefs(MMOBegin, MMOEnd);

100
test/CodeGen/X86/atomic-minmax-i6432.ll
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@ -1,51 +1,67 @@
; RUN: llc -march=x86 -mattr=+cmov -mtriple=i386-pc-linux < %s | FileCheck %s ; RUN: llc -march=x86 -mattr=+cmov -mtriple=i386-pc-linux < %s | FileCheck %s -check-prefix=LINUX
; RUN: llc -march=x86 -mtriple=i386-macosx -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
@sc64 = external global i64 @sc64 = external global i64
define void @atomic_maxmin_i6432() { define void @atomic_maxmin_i6432() {
; CHECK: atomic_maxmin_i6432 ; LINUX: atomic_maxmin_i6432
%1 = atomicrmw max i64* @sc64, i64 5 acquire %1 = atomicrmw max i64* @sc64, i64 5 acquire
; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
; CHECK: cmpl ; LINUX: cmpl
; CHECK: setl ; LINUX: setl
; CHECK: cmpl ; LINUX: cmpl
; CHECK: setl ; LINUX: setl
; CHECK: cmovne ; LINUX: cmovne
; CHECK: cmovne ; LINUX: cmovne
; CHECK: lock ; LINUX: lock
; CHECK-NEXT: cmpxchg8b ; LINUX-NEXT: cmpxchg8b
; CHECK: jne [[LABEL]] ; LINUX: jne [[LABEL]]
%2 = atomicrmw min i64* @sc64, i64 6 acquire %2 = atomicrmw min i64* @sc64, i64 6 acquire
; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
; CHECK: cmpl ; LINUX: cmpl
; CHECK: setg ; LINUX: setg
; CHECK: cmpl ; LINUX: cmpl
; CHECK: setg ; LINUX: setg
; CHECK: cmovne ; LINUX: cmovne
; CHECK: cmovne ; LINUX: cmovne
; CHECK: lock ; LINUX: lock
; CHECK-NEXT: cmpxchg8b ; LINUX-NEXT: cmpxchg8b
; CHECK: jne [[LABEL]] ; LINUX: jne [[LABEL]]
%3 = atomicrmw umax i64* @sc64, i64 7 acquire %3 = atomicrmw umax i64* @sc64, i64 7 acquire
; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
; CHECK: cmpl ; LINUX: cmpl
; CHECK: setb ; LINUX: setb
; CHECK: cmpl ; LINUX: cmpl
; CHECK: setb ; LINUX: setb
; CHECK: cmovne ; LINUX: cmovne
; CHECK: cmovne ; LINUX: cmovne
; CHECK: lock ; LINUX: lock
; CHECK-NEXT: cmpxchg8b ; LINUX-NEXT: cmpxchg8b
; CHECK: jne [[LABEL]] ; LINUX: jne [[LABEL]]
%4 = atomicrmw umin i64* @sc64, i64 8 acquire %4 = atomicrmw umin i64* @sc64, i64 8 acquire
; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
; CHECK: cmpl ; LINUX: cmpl
; CHECK: seta ; LINUX: seta
; CHECK: cmpl ; LINUX: cmpl
; CHECK: seta ; LINUX: seta
; CHECK: cmovne ; LINUX: cmovne
; CHECK: cmovne ; LINUX: cmovne
; CHECK: lock ; LINUX: lock
; CHECK-NEXT: cmpxchg8b ; LINUX-NEXT: cmpxchg8b
; CHECK: jne [[LABEL]] ; LINUX: jne [[LABEL]]
ret void
}
; rdar://12453106
@id = internal global i64 0, align 8
define void @tf_bug(i8* %ptr) nounwind {
; PIC: tf_bug:
; PIC: movl _id-L1$pb(
; PIC: movl (_id-L1$pb)+4(
%tmp1 = atomicrmw add i64* @id, i64 1 seq_cst
%tmp2 = add i64 %tmp1, 1
%tmp3 = bitcast i8* %ptr to i64*
store i64 %tmp2, i64* %tmp3, align 4
ret void ret void
} }