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Use tblgen'd VECTOR_SHUFFLE selection code.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2006-03-20 08:14:16 +00:00
parent f26ba69725
commit e63d746ef6
2 changed files with 2 additions and 19 deletions
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16
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@@ -927,22 +927,6 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: break; default: break;
case ISD::VECTOR_SHUFFLE:
// FIXME: This should be autogenerated from the .td file, it is here for now
// due to bugs in tblgen.
if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
(Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
SDOperand N0;
Select(N0, N->getOperand(0));
Result = CodeGenMap[Op] =
SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
N0), 0);
return;
}
assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
case ISD::SETCC: case ISD::SETCC:
Result = SelectSETCC(Op); Result = SelectSETCC(Op);
return; return;

5
lib/Target/PowerPC/PPCInstrInfo.td
View File

@@ -1034,9 +1034,8 @@ def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vspltw $vD, $vB, $UIMM", VecPerm, "vspltw $vD, $vB, $UIMM", VecPerm,
[/* [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM))]>;
VSPLT_shuffle_mask:$UIMM))*/]>;
// FIXME: ALSO ADD SUPPORT FOR v4i32! // FIXME: ALSO ADD SUPPORT FOR v4i32!
// VX-Form Pseudo Instructions // VX-Form Pseudo Instructions