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[AVX512] Refactoring of avx512_binop_rm multiclass through AVX512_masking.
Added new argrument for AVX512_masking: InstrItinClass and bit isCommutable. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219310 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
c0f7cfa750
commit
e659ba92c8
@ -123,18 +123,21 @@ multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
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string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, dag MaskingRHS,
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string MaskingConstraint = ""> {
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def NAME: AVX512<O, F, Outs, Ins,
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string MaskingConstraint = "",
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InstrItinClass itin = NoItinerary,
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bit IsCommutable = 0> {
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let isCommutable = IsCommutable in
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def NAME: AVX512<O, F, Outs, Ins,
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OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
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"$dst, "#IntelSrcAsm#"}",
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[(set _.RC:$dst, RHS)]>;
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[(set _.RC:$dst, RHS)], itin>;
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// Prefer over VMOV*rrk Pat<>
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let AddedComplexity = 20 in
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def NAME#k: AVX512<O, F, Outs, MaskingIns,
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OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
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"$dst {${mask}}, "#IntelSrcAsm#"}",
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[(set _.RC:$dst, MaskingRHS)]>,
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[(set _.RC:$dst, MaskingRHS)], itin>,
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EVEX_K {
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// In case of the 3src subclass this is overridden with a let.
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string Constraints = MaskingConstraint;
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@ -146,7 +149,8 @@ multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
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[(set _.RC:$dst,
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(vselect _.KRCWM:$mask, RHS,
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(_.VT (bitconvert
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(v16i32 immAllZerosV)))))]>,
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(v16i32 immAllZerosV)))))],
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itin>,
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EVEX_KZ;
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}
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@ -156,13 +160,14 @@ multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
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multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag Ins, string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS> :
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dag RHS, InstrItinClass itin = NoItinerary,
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bit IsCommutable = 0> :
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AVX512_masking_common<O, F, _, Outs, Ins,
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!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
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!con((ins _.KRCWM:$mask), Ins),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(vselect _.KRCWM:$mask, RHS, _.RC:$src0),
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"$src0 = $dst">;
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"$src0 = $dst", itin, IsCommutable>;
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// Similar to AVX512_masking but in this case one of the source operands
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// ($src1) is already tied to $dst so we just use that for the preserved
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@ -2443,92 +2448,32 @@ defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
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// AVX-512 - Integer arithmetic
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//
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multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, RegisterClass KRC,
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RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop, PatFrag scalar_mfrag,
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X86MemOperand x86scalar_mop, string BrdcstStr,
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OpndItins itins, bit IsCommutable = 0> {
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let isCommutable = IsCommutable in
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def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
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itins.rr>, EVEX_4V;
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let AddedComplexity = 30 in {
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let Constraints = "$src0 = $dst" in
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def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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" \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
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RC:$src0)))],
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itins.rr>, EVEX_4V, EVEX_K;
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def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
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"|$dst {${mask}} {z}, $src1, $src2}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
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(OpVT immAllZerosV))))],
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itins.rr>, EVEX_4V, EVEX_KZ;
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}
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X86VectorVTInfo _, OpndItins itins,
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bit IsCommutable = 0> {
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defm rr : AVX512_masking<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2)),
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itins.rr, IsCommutable>,
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AVX512BIBase, EVEX_4V;
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let mayLoad = 1 in {
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def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
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itins.rm>, EVEX_4V;
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let AddedComplexity = 30 in {
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let Constraints = "$src0 = $dst" in
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def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr,
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" \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
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RC:$src0)))],
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itins.rm>, EVEX_4V, EVEX_K;
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def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr,
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" \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
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(OpVT immAllZerosV))))],
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itins.rm>, EVEX_4V, EVEX_KZ;
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}
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def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
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", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
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[(set RC:$dst, (OpNode RC:$src1,
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(OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
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itins.rm>, EVEX_4V, EVEX_B;
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let AddedComplexity = 30 in {
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let Constraints = "$src0 = $dst" in
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def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
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", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
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BrdcstStr, "}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode (OpVT RC:$src1),
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(OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
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RC:$src0)))],
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itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
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def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
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", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
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BrdcstStr, "}"),
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[(set RC:$dst, (OpVT (vselect KRC:$mask,
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(OpNode (OpVT RC:$src1),
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(OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
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(OpVT immAllZerosV))))],
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itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
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}
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defm rm : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1,
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(bitconvert (_.LdFrag addr:$src2)))),
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itins.rm>,
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AVX512BIBase, EVEX_4V;
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defm rmb : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
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"${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr,
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(_.VT (OpNode _.RC:$src1,
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(X86VBroadcast
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(_.ScalarLdFrag addr:$src2)))),
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itins.rm>,
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AVX512BIBase, EVEX_4V, EVEX_B;
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}
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}
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@ -2589,24 +2534,19 @@ multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
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}
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}
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defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
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memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
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defm VPADDDZ : avx512_binop_rm<0xFE, "vpadd", add, v16i32_info,
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SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
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memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
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defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsub", sub, v16i32_info,
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SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
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memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
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defm VPMULLDZ : avx512_binop_rm<0x40, "vpmull", mul, v16i32_info,
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SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
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memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
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defm VPADDQZ : avx512_binop_rm<0xD4, "vpadd", add, v8i64_info,
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SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
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defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
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memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
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defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsub", sub, v8i64_info,
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SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
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@ -2628,39 +2568,31 @@ def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
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(v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
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(VPMULDQZrr VR512:$src1, VR512:$src2)>;
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defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
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memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
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defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v16i32_info,
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SSE_INTALU_ITINS_P, 1>,
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T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
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memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
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defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v8i64_info,
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SSE_INTALU_ITINS_P, 0>,
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T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
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memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
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defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v16i32_info,
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SSE_INTALU_ITINS_P, 1>,
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T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
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memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
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defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v8i64_info,
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SSE_INTALU_ITINS_P, 0>,
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T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
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memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
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defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v16i32_info,
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SSE_INTALU_ITINS_P, 1>,
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T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
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memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
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defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v8i64_info,
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SSE_INTALU_ITINS_P, 0>,
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T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
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memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
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defm VPMINSDZ : avx512_binop_rm<0x39, "vpmins", X86smin, v16i32_info,
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SSE_INTALU_ITINS_P, 1>,
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T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
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memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
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defm VPMINSQZ : avx512_binop_rm<0x39, "vpmins", X86smin, v8i64_info,
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SSE_INTALU_ITINS_P, 0>,
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T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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@ -2793,29 +2725,21 @@ def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
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// AVX-512 Logical Instructions
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//===----------------------------------------------------------------------===//
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defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
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i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
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defm VPANDDZ : avx512_binop_rm<0xDB, "vpand", and, v16i32_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
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i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
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defm VPANDQZ : avx512_binop_rm<0xDB, "vpand", and, v8i64_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
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i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
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defm VPORDZ : avx512_binop_rm<0xEB, "vpor", or, v16i32_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
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i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
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defm VPORQZ : avx512_binop_rm<0xEB, "vpor", or, v8i64_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
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i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
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defm VPXORDZ : avx512_binop_rm<0xEF, "vpxor", xor, v16i32_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
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i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
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defm VPXORQZ : avx512_binop_rm<0xEF, "vpxor", xor, v8i64_info, SSE_BIT_ITINS_P, 1>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
|
||||
memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
|
||||
defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v16i32_info,
|
||||
SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
|
||||
memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
|
||||
defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v8i64_info,
|
||||
SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -714,6 +714,9 @@ class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
|
||||
Requires<[HasAVX512]>;
|
||||
class AVX512BIBase : PD {
|
||||
Domain ExeDomain = SSEPackedInt;
|
||||
}
|
||||
class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
|
||||
|
||||
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Reference in New Issue
Block a user