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Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137223 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-10 17:21:20 +00:00
parent f5ade5d39a
commit e66ef2d5f5
1 changed files with 115 additions and 110 deletions
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225
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -711,82 +711,84 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MFI.getObjectSize(FI), MFI.getObjectSize(FI),
Align); Align);
// tGPR is used sometimes in ARM instructions that need to avoid using switch (RC->getSize()) {
// certain registers. Just treat it as GPR here. Likewise, rGPR. case 4:
if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass if (ARM::GPRRegClass.hasSubClassEq(RC)) {
|| RC == ARM::rGPRRegisterClass) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
RC = ARM::GPRRegisterClass;
switch (RC->getID()) {
case ARM::GPRRegClassID:
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addMemOperand(MMO)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
break; } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
case ARM::SPRRegClassID: AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addMemOperand(MMO)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
break; } else
case ARM::DPRRegClassID: llvm_unreachable("Unknown reg class!");
case ARM::DPR_VFP2RegClassID: break;
case ARM::DPR_8RegClassID: case 8:
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) if (ARM::DPRRegClass.hasSubClassEq(RC)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addMemOperand(MMO)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
break; } else
case ARM::QPRRegClassID: llvm_unreachable("Unknown reg class!");
case ARM::QPR_VFP2RegClassID: break;
case ARM::QPR_8RegClassID: case 16:
if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { if (ARM::QPRRegClass.hasSubClassEq(RC)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
.addFrameIndex(FI).addImm(16) .addFrameIndex(FI).addImm(16)
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO)); .addMemOperand(MMO));
} else { } else {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI) .addFrameIndex(FI)
.addMemOperand(MMO)); .addMemOperand(MMO));
} }
break; } else
case ARM::QQPRRegClassID: llvm_unreachable("Unknown reg class!");
case ARM::QQPR_VFP2RegClassID: break;
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { case 32:
// FIXME: It's possible to only store part of the QQ register if the if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
// spilled def has a sub-register index. if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) // FIXME: It's possible to only store part of the QQ register if the
// spilled def has a sub-register index.
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
.addFrameIndex(FI).addImm(16) .addFrameIndex(FI).addImm(16)
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO)); .addMemOperand(MMO));
} else { } else {
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
.addFrameIndex(FI)) .addFrameIndex(FI))
.addMemOperand(MMO); .addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
} }
break; } else
case ARM::QQQQPRRegClassID: { llvm_unreachable("Unknown reg class!");
MachineInstrBuilder MIB = break;
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) case 64:
.addFrameIndex(FI)) if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
.addMemOperand(MMO); MachineInstrBuilder MIB =
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); .addFrameIndex(FI))
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); .addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
break; MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
} MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
default: AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
llvm_unreachable("Unknown regclass!"); } else
llvm_unreachable("Unknown reg class!");
break;
default:
llvm_unreachable("Unknown reg class!");
} }
} }
@ -860,72 +862,75 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MFI.getObjectSize(FI), MFI.getObjectSize(FI),
Align); Align);
// tGPR is used sometimes in ARM instructions that need to avoid using switch (RC->getSize()) {
// certain registers. Just treat it as GPR here. case 4:
if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass if (ARM::GPRRegClass.hasSubClassEq(RC)) {
|| RC == ARM::rGPRRegisterClass) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
RC = ARM::GPRRegisterClass; .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
switch (RC->getID()) { } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
case ARM::GPRRegClassID: AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
} else
llvm_unreachable("Unknown reg class!");
break; break;
case ARM::SPRRegClassID: case 8:
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) if (ARM::DPRRegClass.hasSubClassEq(RC)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
} else
llvm_unreachable("Unknown reg class!");
break; break;
case ARM::DPRRegClassID: case 16:
case ARM::DPR_VFP2RegClassID: if (ARM::QPRRegClass.hasSubClassEq(RC)) {
case ARM::DPR_8RegClassID: if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
break;
case ARM::QPRRegClassID:
case ARM::QPR_VFP2RegClassID:
case ARM::QPR_8RegClassID:
if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
.addFrameIndex(FI).addImm(16) .addFrameIndex(FI).addImm(16)
.addMemOperand(MMO)); .addMemOperand(MMO));
} else { } else {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
.addFrameIndex(FI) .addFrameIndex(FI)
.addMemOperand(MMO)); .addMemOperand(MMO));
} }
} else
llvm_unreachable("Unknown reg class!");
break; break;
case ARM::QQPRRegClassID: case 32:
case ARM::QQPR_VFP2RegClassID: if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
.addFrameIndex(FI).addImm(16) .addFrameIndex(FI).addImm(16)
.addMemOperand(MMO)); .addMemOperand(MMO));
} else { } else {
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
.addFrameIndex(FI)) .addFrameIndex(FI))
.addMemOperand(MMO); .addMemOperand(MMO);
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
}
} else
llvm_unreachable("Unknown reg class!");
break;
case 64:
if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
.addFrameIndex(FI))
.addMemOperand(MMO);
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
} MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
} else
llvm_unreachable("Unknown reg class!");
break; break;
case ARM::QQQQPRRegClassID: {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
.addFrameIndex(FI))
.addMemOperand(MMO);
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
break;
}
default: default:
llvm_unreachable("Unknown regclass!"); llvm_unreachable("Unknown regclass!");
} }