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Break ARM addrmode4 (load/store multiple base address) into its constituent

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parts. Represent the operation mode as an optional operand instead.
rdar://8614429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-11-03 01:01:43 +00:00
parent 8239daf7c8
commit e6913600c7
10 changed files with 92 additions and 106 deletions
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7
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@@ -113,7 +113,6 @@ public:
SDValue &Offset, SDValue &Opc); SDValue &Offset, SDValue &Opc);
bool SelectAddrMode3Offset(SDNode *Op, SDValue N, bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Opc); SDValue &Offset, SDValue &Opc);
bool SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode);
bool SelectAddrMode5(SDValue N, SDValue &Base, bool SelectAddrMode5(SDValue N, SDValue &Base,
SDValue &Offset); SDValue &Offset);
bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align); bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
@@ -718,12 +717,6 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
return true; return true;
} }
bool ARMDAGToDAGISel::SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode) {
Addr = N;
Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32);
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N, bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
SDValue &Base, SDValue &Offset) { SDValue &Base, SDValue &Offset) {
if (N.getOpcode() != ISD::ADD) { if (N.getOpcode() != ISD::ADD) {

50
lib/Target/ARM/ARMInstrInfo.td
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@@ -444,12 +444,10 @@ def am3offset : Operand<i32>,
let MIOperandInfo = (ops GPR, i32imm); let MIOperandInfo = (ops GPR, i32imm);
} }
// addrmode4 := reg, <mode|W> // ldstm_mode := {ia, ib, da, db}
// //
def addrmode4 : Operand<i32>, def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
ComplexPattern<i32, 2, "SelectAddrMode4", []> { let PrintMethod = "printLdStmModeOperand";
let PrintMethod = "printAddrMode4Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm);
} }
def ARMMemMode5AsmOperand : AsmOperandClass { def ARMMemMode5AsmOperand : AsmOperandClass {
@@ -1171,11 +1169,11 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
// FIXME: Should pc be an implicit operand like PICADD, etc? // FIXME: Should pc be an implicit operand like PICADD, etc?
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def LDM_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$mode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
"ldm${addr:submode}${p}\t$addr!, $dsts", "ldm${mode}${p}\t$Rn!, $dsts",
"$addr.addr = $wb", []>; "$Rn = $wb", []>;
// On non-Darwin platforms R9 is callee-saved. // On non-Darwin platforms R9 is callee-saved.
let isCall = 1, let isCall = 1,
@@ -1423,30 +1421,30 @@ def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
// Store Return State is a system instruction -- for disassembly only // Store Return State is a system instruction -- for disassembly only
let isCodeGenOnly = 1 in { // FIXME: This should not use submode! let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
NoItinerary, "srs${addr:submode}\tsp!, $mode", NoItinerary, "srs${amode}\tsp!, $mode",
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
let Inst{22-20} = 0b110; // W = 1 let Inst{22-20} = 0b110; // W = 1
} }
def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
NoItinerary, "srs${addr:submode}\tsp, $mode", NoItinerary, "srs${amode}\tsp, $mode",
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
let Inst{22-20} = 0b100; // W = 0 let Inst{22-20} = 0b100; // W = 0
} }
// Return From Exception is a system instruction -- for disassembly only // Return From Exception is a system instruction -- for disassembly only
def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
NoItinerary, "rfe${addr:submode}\t$base!", NoItinerary, "rfe${amode}\t$base!",
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
let Inst{22-20} = 0b011; // W = 1 let Inst{22-20} = 0b011; // W = 1
} }
def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
NoItinerary, "rfe${addr:submode}\t$base", NoItinerary, "rfe${amode}\t$base",
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
let Inst{22-20} = 0b001; // W = 0 let Inst{22-20} = 0b001; // W = 0
@@ -1693,30 +1691,30 @@ def STRHT: AI3sthpo<(outs GPR:$base_wb),
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeNone, LdStMulFrm, IIC_iLoad_m, IndexModeNone, LdStMulFrm, IIC_iLoad_m,
"ldm${addr:submode}${p}\t$addr, $dsts", "", []>; "ldm${amode}${p}\t$Rn, $dsts", "", []>;
def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iLoad_mu, IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
"ldm${addr:submode}${p}\t$addr!, $dsts", "ldm${amode}${p}\t$Rn!, $dsts",
"$addr.addr = $wb", []>; "$Rn = $wb", []>;
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p, def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), reglist:$srcs, variable_ops),
IndexModeNone, LdStMulFrm, IIC_iStore_m, IndexModeNone, LdStMulFrm, IIC_iStore_m,
"stm${addr:submode}${p}\t$addr, $srcs", "", []>; "stm${amode}${p}\t$Rn, $srcs", "", []>;
def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), reglist:$srcs, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iStore_mu, IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
"stm${addr:submode}${p}\t$addr!, $srcs", "stm${amode}${p}\t$Rn!, $srcs",
"$addr.addr = $wb", []>; "$Rn = $wb", []>;
} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

10
lib/Target/ARM/ARMInstrNEON.td
View File

@@ -132,14 +132,16 @@ def nModImm : Operand<i32> {
// Use VLDM to load a Q register as a D register pair. // Use VLDM to load a Q register as a D register pair.
// This is a pseudo instruction that is expanded to VLDMD after reg alloc. // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
def VLDMQ def VLDMQ
: PseudoVFPLdStM<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoad_m, "", : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn, ldstm_mode:$mode),
[(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>; IIC_fpLoad_m, "",
[(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
// Use VSTM to store a Q register as a D register pair. // Use VSTM to store a Q register as a D register pair.
// This is a pseudo instruction that is expanded to VSTMD after reg alloc. // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
def VSTMQ def VSTMQ
: PseudoVFPLdStM<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStore_m, "", : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn, ldstm_mode:$mode),
[(store (v2f64 QPR:$src), addrmode4:$addr)]>; IIC_fpStore_m, "",
[(store (v2f64 QPR:$src), GPR:$Rn)]>;
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {

19
lib/Target/ARM/ARMInstrThumb.td
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@@ -540,26 +540,29 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
def tLDM : T1I<(outs), def tLDM : T1I<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts,
variable_ops),
IIC_iLoad_m, IIC_iLoad_m,
"ldm${addr:submode}${p}\t$addr, $dsts", []>, "ldm${amode}${p}\t$Rn, $dsts", []>,
T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
def tLDM_UPD : T1It<(outs tGPR:$wb), def tLDM_UPD : T1It<(outs tGPR:$wb),
(ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts,
variable_ops),
IIC_iLoad_m, IIC_iLoad_m,
"ldm${addr:submode}${p}\t$addr!, $dsts", "ldm${amode}${p}\t$Rn!, $dsts",
"$addr.addr = $wb", []>, "$Rn = $wb", []>,
T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
} // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq } // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
isCodeGenOnly = 1 in isCodeGenOnly = 1 in
def tSTM_UPD : T1It<(outs tGPR:$wb), def tSTM_UPD : T1It<(outs tGPR:$wb),
(ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs,
variable_ops),
IIC_iStore_mu, IIC_iStore_mu,
"stm${addr:submode}${p}\t$addr!, $srcs", "stm${amode}${p}\t$Rn!, $srcs",
"$addr.addr = $wb", []>, "$Rn = $wb", []>,
T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in

26
lib/Target/ARM/ARMInstrThumb2.td
View File

@@ -1246,9 +1246,9 @@ defm t2PLI : T2Ipl<1, 0, "pli">;
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, def t2LDM : T2XI<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), IIC_iLoad_m, reglist:$dsts, variable_ops), IIC_iLoad_m,
"ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> { "ldm${amode}${p}.w\t$Rn, $dsts", []> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
@@ -1257,11 +1257,11 @@ def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
let Inst{20} = 1; // Load let Inst{20} = 1; // Load
} }
def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IIC_iLoad_mu, IIC_iLoad_mu,
"ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", "ldm${amode}${p}.w\t$Rn!, $dsts",
"$addr.addr = $wb", []> { "$Rn = $wb", []> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
@@ -1273,9 +1273,9 @@ def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, def t2STM : T2XI<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), IIC_iStore_m, reglist:$srcs, variable_ops), IIC_iStore_m,
"stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> { "stm${amode}${p}.w\t$Rn, $srcs", []> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
@@ -1284,11 +1284,11 @@ def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
let Inst{20} = 0; // Store let Inst{20} = 0; // Store
} }
def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), reglist:$srcs, variable_ops),
IIC_iStore_m, IIC_iStore_m,
"stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs", "stm${amode}${p}.w\t$Rn!, $srcs",
"$addr.addr = $wb", []> { "$Rn = $wb", []> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
@@ -2437,11 +2437,11 @@ let Defs =
// FIXME: Should pc be an implicit operand like PICADD, etc? // FIXME: Should pc be an implicit operand like PICADD, etc?
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def t2LDM_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IIC_iLoad_mBr, IIC_iLoad_mBr,
"ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", "ldm${amode}${p}.w\t$Rn!, $dsts",
"$addr.addr = $wb", []> { "$Rn = $wb", []> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;
let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'

52
lib/Target/ARM/ARMInstrVFP.td
View File

@@ -85,62 +85,66 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, def VLDMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
variable_ops), IndexModeNone, IIC_fpLoad_m, reglist:$dsts, variable_ops),
"vldm${addr:submode}${p}\t$addr, $dsts", "", []> { IndexModeNone, IIC_fpLoad_m,
"vldm${amode}${p}\t$Rn, $dsts", "", []> {
let Inst{20} = 1; let Inst{20} = 1;
} }
def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, def VLDMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
variable_ops), IndexModeNone, IIC_fpLoad_m, reglist:$dsts, variable_ops),
"vldm${addr:submode}${p}\t$addr, $dsts", "", []> { IndexModeNone, IIC_fpLoad_m,
"vldm${amode}${p}\t$Rn, $dsts", "", []> {
let Inst{20} = 1; let Inst{20} = 1;
} }
def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeUpd, IIC_fpLoad_mu, IndexModeUpd, IIC_fpLoad_mu,
"vldm${addr:submode}${p}\t$addr!, $dsts", "vldm${amode}${p}\t$Rn!, $dsts",
"$addr.addr = $wb", []> { "$Rn = $wb", []> {
let Inst{20} = 1; let Inst{20} = 1;
} }
def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeUpd, IIC_fpLoad_mu, IndexModeUpd, IIC_fpLoad_mu,
"vldm${addr:submode}${p}\t$addr!, $dsts", "vldm${amode}${p}\t$Rn!, $dsts",
"$addr.addr = $wb", []> { "$Rn = $wb", []> {
let Inst{20} = 1; let Inst{20} = 1;
} }
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, def VSTMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
variable_ops), IndexModeNone, IIC_fpStore_m, reglist:$srcs, variable_ops),
"vstm${addr:submode}${p}\t$addr, $srcs", "", []> { IndexModeNone, IIC_fpStore_m,
"vstm${amode}${p}\t$Rn, $srcs", "", []> {
let Inst{20} = 0; let Inst{20} = 0;
} }
def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, def VSTMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
variable_ops), IndexModeNone, IIC_fpStore_m, reglist:$srcs, variable_ops), IndexModeNone,
"vstm${addr:submode}${p}\t$addr, $srcs", "", []> { IIC_fpStore_m,
"vstm${amode}${p}\t$Rn, $srcs", "", []> {
let Inst{20} = 0; let Inst{20} = 0;
} }
def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), reglist:$srcs, variable_ops),
IndexModeUpd, IIC_fpStore_mu, IndexModeUpd, IIC_fpStore_mu,
"vstm${addr:submode}${p}\t$addr!, $srcs", "vstm${amode}${p}\t$Rn!, $srcs",
"$addr.addr = $wb", []> { "$Rn = $wb", []> {
let Inst{20} = 0; let Inst{20} = 0;
} }
def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), reglist:$srcs, variable_ops),
IndexModeUpd, IIC_fpStore_mu, IndexModeUpd, IIC_fpStore_mu,
"vstm${addr:submode}${p}\t$addr!, $srcs", "vstm${amode}${p}\t$Rn!, $srcs",
"$addr.addr = $wb", []> { "$Rn = $wb", []> {
let Inst{20} = 0; let Inst{20} = 0;
} }
} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq

9
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@@ -691,8 +691,8 @@ static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
// MSR/MSRsys: Rm mask=Inst{19-16} // MSR/MSRsys: Rm mask=Inst{19-16}
// BXJ: Rm // BXJ: Rm
// MSRi/MSRsysi: so_imm // MSRi/MSRsysi: so_imm
// SRSW/SRS: addrmode4:$addr mode_imm // SRSW/SRS: ldstm_mode:$amode mode_imm
// RFEW/RFE: addrmode4:$addr Rn // RFEW/RFE: ldstm_mode:$amode Rn
static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@@ -742,13 +742,8 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
NumOpsAdded = 2; NumOpsAdded = 2;
return true; return true;
} }
// SRSW and SRS requires addrmode4:$addr for ${addr:submode}, followed by the
// mode immediate (Inst{4-0}).
if (Opcode == ARM::SRSW || Opcode == ARM::SRS || if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
Opcode == ARM::RFEW || Opcode == ARM::RFE) { Opcode == ARM::RFEW || Opcode == ARM::RFE) {
// ARMInstPrinter::printAddrMode4Operand() prints special mode string
// if the base register is SP; so don't set ARM::SP.
MI.addOperand(MCOperand::CreateReg(0));
ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn)); ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode))); MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));

15
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@@ -290,21 +290,12 @@ void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
<< ImmOffs; << ImmOffs;
} }
void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O, raw_ostream &O,
const char *Modifier) { const char *Modifier) {
const MCOperand &MO2 = MI->getOperand(OpNum+1); ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); .getImm());
if (Modifier && strcmp(Modifier, "submode") == 0) {
O << ARM_AM::getAMSubModeStr(Mode); O << ARM_AM::getAMSubModeStr(Mode);
} else if (Modifier && strcmp(Modifier, "wide") == 0) {
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
if (Mode == ARM_AM::ia)
O << ".w";
} else {
printOperand(MI, OpNum, O);
}
} }
void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,

2
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
View File

@@ -46,7 +46,7 @@ public:
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O); raw_ostream &O);
void printAddrMode4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O,
const char *Modifier = 0); const char *Modifier = 0);
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O,
const char *Modifier = 0); const char *Modifier = 0);

4
utils/TableGen/EDEmitter.cpp
View File

@@ -599,7 +599,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
MISC("addrmode4", "kOperandTypeARMAddrMode4"); // R, I MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
@@ -815,7 +815,7 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
operandTypes.addEntry("kOperandTypeARMAddrMode2Offset"); operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
operandTypes.addEntry("kOperandTypeARMAddrMode3"); operandTypes.addEntry("kOperandTypeARMAddrMode3");
operandTypes.addEntry("kOperandTypeARMAddrMode3Offset"); operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
operandTypes.addEntry("kOperandTypeARMAddrMode4"); operandTypes.addEntry("kOperandTypeARMLdStmMode");
operandTypes.addEntry("kOperandTypeARMAddrMode5"); operandTypes.addEntry("kOperandTypeARMAddrMode5");
operandTypes.addEntry("kOperandTypeARMAddrMode6"); operandTypes.addEntry("kOperandTypeARMAddrMode6");
operandTypes.addEntry("kOperandTypeARMAddrMode6Offset"); operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");