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https://github.com/c64scene-ar/llvm-6502.git
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Addition of a simple two pass scheduler. This version is currently hacked up
for testing and will require target machine info to do a proper scheduling. The simple scheduler can be turned on using -sched=simple (defaults to -sched=none) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23455 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey
parent
6bc7e513d5
commit
e6b90fba4a
@ -7,8 +7,9 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple code linearizer for DAGs. This is not a very good
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// way to emit code, but gets working code quickly.
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// This implements a simple two pass scheduler. The first pass attempts to push
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// backward any lengthy instructions and critical paths. The second pass packs
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// instructions into semi-optimal time slots.
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//
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//===----------------------------------------------------------------------===//
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@ -22,8 +23,29 @@
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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// Style of scheduling to use.
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enum ScheduleChoices {
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noScheduling,
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simpleScheduling,
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};
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} // namespace
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cl::opt<ScheduleChoices> ScheduleStyle("sched",
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cl::desc("Choose scheduling style"),
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cl::init(noScheduling),
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cl::values(
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clEnumValN(noScheduling, "none",
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"Trivial emission with no analysis"),
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clEnumValN(simpleScheduling, "simple",
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"Minimize critical path and maximize processor utilization"),
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clEnumValEnd));
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#ifndef NDEBUG
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static cl::opt<bool>
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ViewDAGs("view-sched-dags", cl::Hidden,
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@ -33,76 +55,681 @@ static const bool ViewDAGs = 0;
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#endif
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namespace {
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class SimpleSched {
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SelectionDAG &DAG;
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MachineBasicBlock *BB;
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const MRegisterInfo &MRI;
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SSARegMap *RegMap;
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MachineConstantPool *ConstPool;
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//===----------------------------------------------------------------------===//
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///
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/// BitsIterator - Provides iteration through individual bits in a bit vector.
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///
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template<class T>
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class BitsIterator {
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private:
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T Bits; // Bits left to iterate through
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std::map<SDNode *, unsigned> EmittedOps;
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public:
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SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
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: DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
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MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()),
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ConstPool(BB->getParent()->getConstantPool()) {
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assert(&TII && "Target doesn't provide instr info?");
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assert(&MRI && "Target doesn't provide register info?");
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public:
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/// Ctor.
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BitsIterator(T Initial) : Bits(Initial) {}
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/// Next - Returns the next bit set or zero if exhausted.
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inline T Next() {
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// Get the rightmost bit set
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T Result = Bits & -Bits;
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// Remove from rest
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Bits &= ~Result;
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// Return single bit or zero
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return Result;
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}
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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/// ResourceTally - Manages the use of resources over time intervals. Each
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/// item (slot) in the tally vector represents the resources used at a given
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/// moment. A bit set to 1 indicates that a resource is in use, otherwise
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/// available. An assumption is made that the tally is large enough to schedule
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/// all current instructions (asserts otherwise.)
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///
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template<class T>
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class ResourceTally {
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private:
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std::vector<T> Tally; // Resources used per slot
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typedef typename std::vector<T>::iterator Iter;
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// Tally iterator
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/// AllInUse - Test to see if all of the resources in the slot are busy (set.)
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inline bool AllInUse(Iter Cursor, unsigned ResourceSet) {
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return (*Cursor & ResourceSet) == ResourceSet;
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}
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/// Skip - Skip over slots that use all of the specified resource (all are
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/// set.)
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Iter Skip(Iter Cursor, unsigned ResourceSet) {
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assert(ResourceSet && "At least one resource bit needs to bet set");
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// Continue to the end
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while (true) {
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// Break out if one of the resource bits is not set
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if (!AllInUse(Cursor, ResourceSet)) return Cursor;
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// Try next slot
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Cursor++;
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assert(Cursor < Tally.end() && "Tally is not large enough for schedule");
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}
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}
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MachineBasicBlock *Run() {
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Emit(DAG.getRoot());
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return BB;
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/// FindSlots - Starting from Begin, locate N consecutive slots where at least
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/// one of the resource bits is available. Returns the address of first slot.
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Iter FindSlots(Iter Begin, unsigned N, unsigned ResourceSet,
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unsigned &Resource) {
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// Track position
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Iter Cursor = Begin;
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// Try all possible slots forward
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while (true) {
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// Skip full slots
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Cursor = Skip(Cursor, ResourceSet);
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// Determine end of interval
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Iter End = Cursor + N;
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assert(End <= Tally.end() && "Tally is not large enough for schedule");
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// Iterate thru each resource
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BitsIterator<T> Resources(ResourceSet & ~*Cursor);
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while (unsigned Res = Resources.Next()) {
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// Check if resource is available for next N slots
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// Break out if resource is busy
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Iter Interval = Cursor;
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for (; Interval < End && !(*Interval & Res); Interval++) {}
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// If available for interval, return where and which resource
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if (Interval == End) {
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Resource = Res;
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return Cursor;
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}
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// Otherwise, check if worth checking other resources
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if (AllInUse(Interval, ResourceSet)) {
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// Start looking beyond interval
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Cursor = Interval;
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break;
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}
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}
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Cursor++;
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}
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}
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private:
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unsigned Emit(SDOperand Op);
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/// Reserve - Mark busy (set) the specified N slots.
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void Reserve(Iter Begin, unsigned N, unsigned Resource) {
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// Determine end of interval
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Iter End = Begin + N;
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assert(End <= Tally.end() && "Tally is not large enough for schedule");
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// Set resource bit in each slot
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for (; Begin < End; Begin++)
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*Begin |= Resource;
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}
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public:
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/// Initialize - Resize and zero the tally to the specified number of time
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/// slots.
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inline void Initialize(unsigned N) {
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Tally.assign(N, 0); // Initialize tally to all zeros.
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}
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// FindAndReserve - Locate and mark busy (set) N bits started at slot I, using
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// ResourceSet for choices.
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unsigned FindAndReserve(unsigned I, unsigned N, unsigned ResourceSet) {
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// Which resource used
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unsigned Resource;
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// Find slots for instruction.
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Iter Where = FindSlots(Tally.begin() + I, N, ResourceSet, Resource);
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// Reserve the slots
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Reserve(Where, N, Resource);
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// Return time slot (index)
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return Where - Tally.begin();
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}
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// This struct tracks information used to schedule the a node.
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struct ScheduleInfo {
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SDOperand Op; // Operand information
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unsigned Latency; // Cycles to complete instruction
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unsigned ResourceSet; // Bit vector of usable resources
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bool IsBoundary; // Do not shift passed this instruction.
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unsigned Slot; // Operand's time slot
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// Ctor.
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ScheduleInfo(SDOperand op)
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: Op(op)
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, Latency(0)
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, ResourceSet(0)
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, IsBoundary(false)
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, Slot(0)
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{}
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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class SimpleSched {
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private:
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// TODO - get ResourceSet from TII
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enum {
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RSInteger = 0x3, // Two integer units
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RSFloat = 0xC, // Two float units
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RSLoadStore = 0x30, // Two load store units
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RSOther = 0 // Processing unit independent
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};
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MachineBasicBlock *BB; // Current basic block
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SelectionDAG &DAG; // DAG of the current basic block
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const TargetMachine &TM; // Target processor
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const TargetInstrInfo &TII; // Target instruction information
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const MRegisterInfo &MRI; // Target processor register information
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SSARegMap *RegMap; // Virtual/real register map
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MachineConstantPool *ConstPool; // Target constant pool
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std::vector<ScheduleInfo> Operands; // All operands to be scheduled
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std::vector<ScheduleInfo*> Ordering; // Emit ordering of operands
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std::map<SDNode *, int> Visited; // Operands that have been visited
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ResourceTally<unsigned> Tally; // Resource usage tally
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unsigned NSlots; // Total latency
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std::map<SDNode *, unsigned>VRMap; // Operand to VR map
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static const unsigned NotFound = ~0U; // Search marker
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public:
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// Ctor.
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SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
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: BB(bb), DAG(D), TM(D.getTarget()), TII(*TM.getInstrInfo()),
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MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()),
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ConstPool(BB->getParent()->getConstantPool()),
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NSlots(0) {
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assert(&TII && "Target doesn't provide instr info?");
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assert(&MRI && "Target doesn't provide register info?");
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}
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// Run - perform scheduling.
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MachineBasicBlock *Run() {
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Schedule();
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return BB;
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}
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private:
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static bool isFlagDefiner(SDOperand Op) { return isFlagDefiner(Op.Val); }
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static bool isFlagUser(SDOperand Op) { return isFlagUser(Op.Val); }
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static bool isFlagDefiner(SDNode *A);
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static bool isFlagUser(SDNode *A);
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static bool isDefiner(SDNode *A, SDNode *B);
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static bool isPassiveOperand(SDOperand Op);
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void IncludeOperand(SDOperand Op);
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void VisitAll();
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void Schedule();
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void GatherOperandInfo();
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bool isStrongDependency(SDOperand A, SDOperand B) {
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return isStrongDependency(A.Val, B.Val);
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}
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bool isWeakDependency(SDOperand A, SDOperand B) {
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return isWeakDependency(A.Val, B.Val);
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}
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static bool isStrongDependency(SDNode *A, SDNode *B);
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static bool isWeakDependency(SDNode *A, SDNode *B);
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void ScheduleBackward();
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void ScheduleForward();
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void EmitAll();
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void EmitFlagUsers(SDOperand Op);
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static unsigned CountResults(SDOperand Op);
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static unsigned CountOperands(SDOperand Op);
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unsigned CreateVirtualRegisters(SDOperand Op, MachineInstr *MI,
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unsigned NumResults,
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const TargetInstrDescriptor &II);
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unsigned Emit(SDOperand A);
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void printSI(std::ostream &O, ScheduleInfo *SI) const ;
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void print(std::ostream &O) const ;
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inline void dump(const char *tag) const { std::cerr << tag; dump(); }
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void dump() const;
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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class FlagUserIterator {
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private:
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SDNode *Definer; // Node defining flag
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SDNode::use_iterator UI; // User node iterator
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SDNode::use_iterator E; // End of user nodes
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unsigned MinRes; // Minimum flag result
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public:
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// Ctor.
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FlagUserIterator(SDNode *D)
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: Definer(D)
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, UI(D->use_begin())
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, E(D->use_end())
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, MinRes(D->getNumValues()) {
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// Find minimum flag result.
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while (MinRes && D->getValueType(MinRes - 1) == MVT::Flag) --MinRes;
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}
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/// isFlagUser - Return true if node uses definer's flag.
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bool isFlagUser(SDNode *U) {
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// For each operand (in reverse to only look at flags)
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for (unsigned N = U->getNumOperands(); 0 < N--;) {
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// Get operand
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SDOperand Op = U->getOperand(N);
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// Not user if there are no flags
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if (Op.getValueType() != MVT::Flag) return false;
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// Return true if it is one of the flag results
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if (Op.Val == Definer && Op.ResNo >= MinRes) return true;
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}
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// Not a flag user
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return false;
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}
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SDNode *next() {
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// Continue to next user
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while (UI != E) {
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// Next user node
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SDNode *User = *UI++;
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// Return true if is a flag user
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if (isFlagUser(User)) return User;
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}
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// No more user nodes
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return NULL;
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}
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};
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} // namespace
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//===----------------------------------------------------------------------===//
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/// isFlagDefiner - Returns true if the operand defines a flag result.
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bool SimpleSched::isFlagDefiner(SDNode *A) {
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unsigned N = A->getNumValues();
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return N && A->getValueType(N - 1) == MVT::Flag;
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}
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unsigned SimpleSched::Emit(SDOperand Op) {
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// Check to see if we have already emitted this. If so, return the value
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// already emitted. Note that if a node has a single use it cannot be
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// revisited, so don't bother putting it in the map.
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unsigned *OpSlot;
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if (Op.Val->hasOneUse()) {
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OpSlot = 0; // No reuse possible.
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} else {
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std::map<SDNode *, unsigned>::iterator OpI = EmittedOps.lower_bound(Op.Val);
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if (OpI != EmittedOps.end() && OpI->first == Op.Val)
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return OpI->second + Op.ResNo;
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OpSlot = &EmittedOps.insert(OpI, std::make_pair(Op.Val, 0))->second;
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/// isFlagUser - Returns true if the operand uses a flag result.
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///
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bool SimpleSched::isFlagUser(SDNode *A) {
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unsigned N = A->getNumOperands();
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return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
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}
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/// isDefiner - Return true if Node A is a definder for B.
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///
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bool SimpleSched::isDefiner(SDNode *A, SDNode *B) {
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for (unsigned i = 0, N = B->getNumOperands(); i < N; i++) {
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if (B->getOperand(i).Val == A) return true;
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}
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return false;
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}
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/// isPassiveOperand - Return true if the operand is a non-scheduled leaf
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/// operand.
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bool SimpleSched::isPassiveOperand(SDOperand Op) {
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if (isa<ConstantSDNode>(Op)) return true;
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if (isa<RegisterSDNode>(Op)) return true;
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if (isa<GlobalAddressSDNode>(Op)) return true;
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if (isa<BasicBlockSDNode>(Op)) return true;
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if (isa<FrameIndexSDNode>(Op)) return true;
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if (isa<ConstantPoolSDNode>(Op)) return true;
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if (isa<ExternalSymbolSDNode>(Op)) return true;
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return false;
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}
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/// IncludeOperand - Add operand to ScheduleInfo vector.
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///
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void SimpleSched::IncludeOperand(SDOperand Op) {
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// Ignore entry node
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if (Op.getOpcode() == ISD::EntryToken) return;
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// Check current count for operand
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int Count = Visited[Op.Val];
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// If the operand is already in list
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if (Count < 0) return;
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// If this the first time then get count
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if (!Count) Count = Op.Val->use_size();
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// Decrement count to indicate a visit
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Count--;
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// If count has gone to zero then add operand to list
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if (!Count) {
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// Add operand
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Operands.push_back(ScheduleInfo(Op));
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// indicate operand has been added
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Count--;
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}
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// Mark as visited with new count
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Visited[Op.Val] = Count;
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}
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/// VisitAll - Visit each operand breadth-wise to produce an initial ordering.
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/// Note that the ordering in the Operands vector is reversed.
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void SimpleSched::VisitAll() {
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// Add first element to list
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Operands.push_back(DAG.getRoot());
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for (unsigned i = 0; i < Operands.size(); i++) { // note: size() varies
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// Get next operand. Need copy because Operands vector is growing and
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// addresses can be ScheduleInfo changing.
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SDOperand Op = Operands[i].Op;
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// Get the number of real operands
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unsigned NodeOperands = CountOperands(Op);
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// Get the total number of operands
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unsigned NumOperands = Op.getNumOperands();
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// Visit all operands skipping the Other operand if present
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for (unsigned i = NumOperands; 0 < i--;) {
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SDOperand OpI = Op.getOperand(i);
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// Ignore passive operands
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if (isPassiveOperand(OpI)) continue;
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// Check out operand
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IncludeOperand(OpI);
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}
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}
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// Add entry node last (IncludeOperand filters entry nodes)
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if (DAG.getEntryNode().Val != DAG.getRoot().Val)
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Operands.push_back(DAG.getEntryNode());
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}
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/// GatherOperandInfo - Get latency and resource information about each operand.
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///
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void SimpleSched::GatherOperandInfo() {
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// Add addresses of operand info to ordering vector
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// Get number of operands
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unsigned N = Operands.size();
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// FIXME: This is an ugly (but temporary!) hack to test the scheduler before
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// we have real target info.
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// For each operand being scheduled
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for (unsigned i = 0; i < N; i++) {
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ScheduleInfo* SI = &Operands[N - i - 1];
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SDOperand Op = SI->Op;
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MVT::ValueType VT = Op.Val->getValueType(0);
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if (Op.isTargetOpcode()) {
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MachineOpCode TOpc = Op.getTargetOpcode();
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// FIXME SI->Latency = std::max(1, TII.maxLatency(TOpc));
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// FIXME SI->ResourceSet = TII.resources(TOpc);
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||||
// There is a cost for keeping values across a call.
|
||||
SI->IsBoundary = TII.isCall(TOpc);
|
||||
|
||||
if (TII.isLoad(TOpc)) {
|
||||
SI->ResourceSet = RSLoadStore;
|
||||
SI->Latency = 5;
|
||||
} else if (TII.isStore(TOpc)) {
|
||||
SI->ResourceSet = RSLoadStore;
|
||||
SI->Latency = 2;
|
||||
} else if (MVT::isInteger(VT)) {
|
||||
SI->ResourceSet = RSInteger;
|
||||
SI->Latency = 2;
|
||||
} else if (MVT::isFloatingPoint(VT)) {
|
||||
SI->ResourceSet = RSFloat;
|
||||
SI->Latency = 3;
|
||||
} else {
|
||||
SI->ResourceSet = RSOther;
|
||||
SI->Latency = 0;
|
||||
}
|
||||
} else {
|
||||
if (MVT::isInteger(VT)) {
|
||||
SI->ResourceSet = RSInteger;
|
||||
SI->Latency = 2;
|
||||
} else if (MVT::isFloatingPoint(VT)) {
|
||||
SI->ResourceSet = RSFloat;
|
||||
SI->Latency = 3;
|
||||
} else {
|
||||
SI->ResourceSet = RSOther;
|
||||
SI->Latency = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// Add one slot for the instruction itself
|
||||
SI->Latency++;
|
||||
|
||||
// Sum up all the latencies for max tally size
|
||||
NSlots += SI->Latency;
|
||||
|
||||
// Place in initial sorted order
|
||||
// FIXME - PUNT - ignore flag users
|
||||
if (!isFlagUser(Op)) Ordering.push_back(SI);
|
||||
}
|
||||
}
|
||||
|
||||
/// isStrongDependency - Return true if operand A has results used by operand B.
|
||||
/// I.E., B must wait for latency of A.
|
||||
bool SimpleSched::isStrongDependency(SDNode *A, SDNode *B) {
|
||||
// If A defines for B then it's a strong dependency
|
||||
if (isDefiner(A, B)) return true;
|
||||
// If A defines a flag then it's users are part of the dependency
|
||||
if (isFlagDefiner(A)) {
|
||||
// Check each flag user
|
||||
FlagUserIterator FI(A);
|
||||
while (SDNode *User = FI.next()) {
|
||||
// If flag user has strong dependency so does B
|
||||
if (isStrongDependency(User, B)) return true;
|
||||
}
|
||||
}
|
||||
// If B defines a flag then it's users are part of the dependency
|
||||
if (isFlagDefiner(B)) {
|
||||
// Check each flag user
|
||||
FlagUserIterator FI(B);
|
||||
while (SDNode *User = FI.next()) {
|
||||
// If flag user has strong dependency so does B
|
||||
if (isStrongDependency(A, User)) return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/// isWeakDependency Return true if operand A produces a result that will
|
||||
/// conflict with operands of B.
|
||||
bool SimpleSched::isWeakDependency(SDNode *A, SDNode *B) {
|
||||
// TODO check for conflicting real registers and aliases
|
||||
return A->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
|
||||
}
|
||||
|
||||
/// ScheduleBackward - Schedule instructions so that any long latency
|
||||
/// instructions and the critical path get pushed back in time. Time is run in
|
||||
/// reverse to allow code reuse of the Tally and eliminate the overhead of
|
||||
/// biasing every slot indices against NSlots.
|
||||
void SimpleSched::ScheduleBackward() {
|
||||
// Size and clear the resource tally
|
||||
Tally.Initialize(NSlots);
|
||||
// Get number of operands to schedule
|
||||
unsigned N = Ordering.size();
|
||||
|
||||
// For each operand being scheduled
|
||||
for (unsigned i = N; 0 < i--;) {
|
||||
ScheduleInfo *SI = Ordering[i];
|
||||
// Track insertion
|
||||
unsigned Slot = NotFound;
|
||||
|
||||
// Compare against those previously scheduled operands
|
||||
for (unsigned j = i + 1; j < N; j++) {
|
||||
// Get following instruction
|
||||
ScheduleInfo *Other = Ordering[j];
|
||||
|
||||
// Check dependency against previously inserted operands
|
||||
if (isStrongDependency(SI->Op, Other->Op)) {
|
||||
Slot = Other->Slot + Other->Latency;
|
||||
break;
|
||||
} else if (SI->IsBoundary || Other->IsBoundary ||
|
||||
isWeakDependency(SI->Op, Other->Op)) {
|
||||
Slot = Other->Slot;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// If independent of others (or first entry)
|
||||
if (Slot == NotFound) Slot = 0;
|
||||
|
||||
// Find a slot where the needed resources are available
|
||||
if (SI->ResourceSet)
|
||||
Slot = Tally.FindAndReserve(Slot, SI->Latency, SI->ResourceSet);
|
||||
|
||||
// Set operand slot
|
||||
SI->Slot = Slot;
|
||||
|
||||
// Insert sort based on slot
|
||||
unsigned j = i + 1;
|
||||
for (; j < N; j++) {
|
||||
// Get following instruction
|
||||
ScheduleInfo *Other = Ordering[j];
|
||||
// Should we look further
|
||||
if (Slot >= Other->Slot) break;
|
||||
// Shuffle other into ordering
|
||||
Ordering[j - 1] = Other;
|
||||
}
|
||||
// Insert operand in proper slot
|
||||
if (j != i + 1) Ordering[j - 1] = SI;
|
||||
}
|
||||
}
|
||||
|
||||
/// ScheduleForward - Schedule instructions to maximize packing.
|
||||
///
|
||||
void SimpleSched::ScheduleForward() {
|
||||
// Size and clear the resource tally
|
||||
Tally.Initialize(NSlots);
|
||||
// Get number of operands to schedule
|
||||
unsigned N = Ordering.size();
|
||||
|
||||
// For each operand being scheduled
|
||||
for (unsigned i = 0; i < N; i++) {
|
||||
ScheduleInfo *SI = Ordering[i];
|
||||
// Track insertion
|
||||
unsigned Slot = NotFound;
|
||||
|
||||
// Compare against those previously scheduled operands
|
||||
for (unsigned j = i; 0 < j--;) {
|
||||
// Get following instruction
|
||||
ScheduleInfo *Other = Ordering[j];
|
||||
|
||||
// Check dependency against previously inserted operands
|
||||
if (isStrongDependency(Other->Op, SI->Op)) {
|
||||
Slot = Other->Slot + Other->Latency;
|
||||
break;
|
||||
} else if (SI->IsBoundary || Other->IsBoundary ||
|
||||
isWeakDependency(Other->Op, SI->Op)) {
|
||||
Slot = Other->Slot;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// If independent of others (or first entry)
|
||||
if (Slot == NotFound) Slot = 0;
|
||||
|
||||
// Find a slot where the needed resources are available
|
||||
if (SI->ResourceSet)
|
||||
Slot = Tally.FindAndReserve(Slot, SI->Latency, SI->ResourceSet);
|
||||
|
||||
// Set operand slot
|
||||
SI->Slot = Slot;
|
||||
|
||||
// Insert sort based on slot
|
||||
unsigned j = i;
|
||||
for (; 0 < j--;) {
|
||||
// Get following instruction
|
||||
ScheduleInfo *Other = Ordering[j];
|
||||
// Should we look further
|
||||
if (Slot >= Other->Slot) break;
|
||||
// Shuffle other into ordering
|
||||
Ordering[j + 1] = Other;
|
||||
}
|
||||
// Insert operand in proper slot
|
||||
if (j != i) Ordering[j + 1] = SI;
|
||||
}
|
||||
}
|
||||
|
||||
/// EmitAll - Emit all operands in schedule sorted order.
|
||||
///
|
||||
void SimpleSched::EmitAll() {
|
||||
// For each operand in the ordering
|
||||
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
||||
// Get the scheduling info
|
||||
ScheduleInfo *SI = Ordering[i];
|
||||
// Get the operand
|
||||
SDOperand Op = SI->Op;
|
||||
// Emit the operand
|
||||
Emit(Op);
|
||||
// FIXME - PUNT - If Op defines a flag then it's users need to be emitted now
|
||||
if (isFlagDefiner(Op)) EmitFlagUsers(Op);
|
||||
}
|
||||
}
|
||||
|
||||
/// EmitFlagUsers - Emit users of operands flag.
|
||||
///
|
||||
void SimpleSched::EmitFlagUsers(SDOperand Op) {
|
||||
// Check each flag user
|
||||
FlagUserIterator FI(Op.Val);
|
||||
while (SDNode *User = FI.next()) {
|
||||
// Construct user node as operand
|
||||
SDOperand OpU(User, 0);
|
||||
// Emit user node
|
||||
Emit(OpU);
|
||||
// If user defines a flag then it's users need to be emitted now
|
||||
if (isFlagDefiner(User)) EmitFlagUsers(OpU);
|
||||
}
|
||||
}
|
||||
|
||||
/// CountResults - The results of target nodes have register or immediate
|
||||
/// operands first, then an optional chain, and optional flag operands (which do
|
||||
/// not go into the machine instrs.)
|
||||
unsigned SimpleSched::CountResults(SDOperand Op) {
|
||||
unsigned N = Op.Val->getNumValues();
|
||||
while (N && Op.Val->getValueType(N - 1) == MVT::Flag)
|
||||
--N;
|
||||
if (N && Op.Val->getValueType(N - 1) == MVT::Other)
|
||||
--N; // Skip over chain result.
|
||||
return N;
|
||||
}
|
||||
|
||||
/// CountOperands The inputs to target nodes have any actual inputs first,
|
||||
/// followed by an optional chain operand, then flag operands. Compute the
|
||||
/// number of actual operands that will go into the machine instr.
|
||||
unsigned SimpleSched::CountOperands(SDOperand Op) {
|
||||
unsigned N = Op.getNumOperands();
|
||||
while (N && Op.getOperand(N - 1).getValueType() == MVT::Flag)
|
||||
--N;
|
||||
if (N && Op.getOperand(N - 1).getValueType() == MVT::Other)
|
||||
--N; // Ignore chain if it exists.
|
||||
return N;
|
||||
}
|
||||
|
||||
/// CreateVirtualRegisters - Add result register values for things that are
|
||||
/// defined by this instruction.
|
||||
unsigned SimpleSched::CreateVirtualRegisters(SDOperand Op, MachineInstr *MI,
|
||||
unsigned NumResults,
|
||||
const TargetInstrDescriptor &II) {
|
||||
// Create the result registers for this node and add the result regs to
|
||||
// the machine instruction.
|
||||
const TargetOperandInfo *OpInfo = II.OpInfo;
|
||||
unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
|
||||
MI->addRegOperand(ResultReg, MachineOperand::Def);
|
||||
for (unsigned i = 1; i != NumResults; ++i) {
|
||||
assert(OpInfo[i].RegClass && "Isn't a register operand!");
|
||||
MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[0].RegClass),
|
||||
MachineOperand::Def);
|
||||
}
|
||||
return ResultReg;
|
||||
}
|
||||
|
||||
/// Emit - Generate machine code for an operand and needed dependencies.
|
||||
///
|
||||
unsigned SimpleSched::Emit(SDOperand Op) {
|
||||
std::map<SDNode *, unsigned>::iterator OpI = VRMap.lower_bound(Op.Val);
|
||||
if (OpI != VRMap.end() && OpI->first == Op.Val)
|
||||
return OpI->second + Op.ResNo;
|
||||
unsigned &OpSlot = VRMap.insert(OpI, std::make_pair(Op.Val, 0))->second;
|
||||
|
||||
unsigned ResultReg = 0;
|
||||
if (Op.isTargetOpcode()) {
|
||||
unsigned Opc = Op.getTargetOpcode();
|
||||
const TargetInstrDescriptor &II = TII.get(Opc);
|
||||
|
||||
// The results of target nodes have register or immediate operands first,
|
||||
// then an optional chain, and optional flag operands (which do not go into
|
||||
// the machine instrs).
|
||||
unsigned NumResults = Op.Val->getNumValues();
|
||||
while (NumResults && Op.Val->getValueType(NumResults-1) == MVT::Flag)
|
||||
--NumResults;
|
||||
if (NumResults && Op.Val->getValueType(NumResults-1) == MVT::Other)
|
||||
--NumResults; // Skip over chain result.
|
||||
|
||||
// The inputs to target nodes have any actual inputs first, followed by an
|
||||
// optional chain operand, then flag operands. Compute the number of actual
|
||||
// operands that will go into the machine instr.
|
||||
unsigned NodeOperands = Op.getNumOperands();
|
||||
while (NodeOperands &&
|
||||
Op.getOperand(NodeOperands-1).getValueType() == MVT::Flag)
|
||||
--NodeOperands;
|
||||
|
||||
if (NodeOperands && // Ignore chain if it exists.
|
||||
Op.getOperand(NodeOperands-1).getValueType() == MVT::Other)
|
||||
--NodeOperands;
|
||||
|
||||
unsigned NumMIOperands = NodeOperands+NumResults;
|
||||
unsigned NumResults = CountResults(Op);
|
||||
unsigned NodeOperands = CountOperands(Op);
|
||||
unsigned NumMIOperands = NodeOperands + NumResults;
|
||||
#ifndef NDEBUG
|
||||
assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
|
||||
"#operands for dag node doesn't match .td file!");
|
||||
@ -113,24 +740,14 @@ unsigned SimpleSched::Emit(SDOperand Op) {
|
||||
|
||||
// Add result register values for things that are defined by this
|
||||
// instruction.
|
||||
if (NumResults) {
|
||||
// Create the result registers for this node and add the result regs to
|
||||
// the machine instruction.
|
||||
const TargetOperandInfo *OpInfo = II.OpInfo;
|
||||
ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
|
||||
MI->addRegOperand(ResultReg, MachineOperand::Def);
|
||||
for (unsigned i = 1; i != NumResults; ++i) {
|
||||
assert(OpInfo[i].RegClass && "Isn't a register operand!");
|
||||
MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[0].RegClass),
|
||||
MachineOperand::Def);
|
||||
}
|
||||
}
|
||||
if (NumResults) ResultReg = CreateVirtualRegisters(Op, MI, NumResults, II);
|
||||
|
||||
// If there is a token chain operand, emit it first, as a hack to get avoid
|
||||
// really bad cases.
|
||||
if (Op.getNumOperands() > NodeOperands &&
|
||||
Op.getOperand(NodeOperands).getValueType() == MVT::Other)
|
||||
Op.getOperand(NodeOperands).getValueType() == MVT::Other) {
|
||||
Emit(Op.getOperand(NodeOperands));
|
||||
}
|
||||
|
||||
// Emit all of the actual operands of this instruction, adding them to the
|
||||
// instruction as appropriate.
|
||||
@ -179,7 +796,7 @@ unsigned SimpleSched::Emit(SDOperand Op) {
|
||||
unsigned i = NodeOperands;
|
||||
if (Op.getOperand(i).getValueType() == MVT::Other)
|
||||
++i; // the chain is already selected.
|
||||
for (; i != Op.getNumOperands(); ++i) {
|
||||
for (unsigned N = Op.getNumOperands(); i < N; i++) {
|
||||
assert(Op.getOperand(i).getValueType() == MVT::Flag &&
|
||||
"Must be flag operands!");
|
||||
Emit(Op.getOperand(i));
|
||||
@ -201,17 +818,22 @@ unsigned SimpleSched::Emit(SDOperand Op) {
|
||||
assert(0 && "This target-independent node should have been selected!");
|
||||
case ISD::EntryToken: break;
|
||||
case ISD::TokenFactor:
|
||||
for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
|
||||
for (unsigned i = 0, N = Op.getNumOperands(); i < N; i++) {
|
||||
Emit(Op.getOperand(i));
|
||||
}
|
||||
break;
|
||||
case ISD::CopyToReg: {
|
||||
SDOperand FlagOp;
|
||||
if (Op.getNumOperands() == 4)
|
||||
if (Op.getNumOperands() == 4) {
|
||||
FlagOp = Op.getOperand(3);
|
||||
if (Op.getOperand(0).Val != FlagOp.Val)
|
||||
}
|
||||
if (Op.getOperand(0).Val != FlagOp.Val) {
|
||||
Emit(Op.getOperand(0)); // Emit the chain.
|
||||
}
|
||||
unsigned Val = Emit(Op.getOperand(2));
|
||||
if (FlagOp.Val) Emit(FlagOp);
|
||||
if (FlagOp.Val) {
|
||||
Emit(FlagOp);
|
||||
}
|
||||
MRI.copyRegToReg(*BB, BB->end(),
|
||||
cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
|
||||
RegMap->getRegClass(Val));
|
||||
@ -245,13 +867,82 @@ unsigned SimpleSched::Emit(SDOperand Op) {
|
||||
}
|
||||
}
|
||||
|
||||
if (OpSlot) *OpSlot = ResultReg;
|
||||
OpSlot = ResultReg;
|
||||
return ResultReg+Op.ResNo;
|
||||
}
|
||||
|
||||
/// Schedule - Order operands according to selected style.
|
||||
///
|
||||
void SimpleSched::Schedule() {
|
||||
switch (ScheduleStyle) {
|
||||
case simpleScheduling:
|
||||
// Breadth first walk of DAG
|
||||
VisitAll();
|
||||
// Get latency and resource requirements
|
||||
GatherOperandInfo();
|
||||
// Don't waste time if is only entry and return
|
||||
if (Operands.size() > 2) {
|
||||
DEBUG(dump("Pre-"));
|
||||
// Push back long instructions and critical path
|
||||
ScheduleBackward();
|
||||
DEBUG(dump("Mid-"));
|
||||
// Pack instructions to maximize resource utilization
|
||||
ScheduleForward();
|
||||
DEBUG(dump("Post-"));
|
||||
// Emit in scheduled order
|
||||
EmitAll();
|
||||
break;
|
||||
} // fall thru
|
||||
case noScheduling:
|
||||
// Emit instructions in using a DFS from the exit root
|
||||
Emit(DAG.getRoot());
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/// Pick a safe ordering and emit instructions for each target node in the
|
||||
/// graph.
|
||||
/// printSI - Print schedule info.
|
||||
///
|
||||
void SimpleSched::printSI(std::ostream &O, ScheduleInfo *SI) const {
|
||||
#ifndef NDEBUG
|
||||
using namespace std;
|
||||
SDOperand Op = SI->Op;
|
||||
O << " "
|
||||
<< hex << Op.Val
|
||||
<< ", RS=" << SI->ResourceSet
|
||||
<< ", Lat=" << SI->Latency
|
||||
<< ", Slot=" << SI->Slot
|
||||
<< ", ARITY=(" << Op.getNumOperands() << ","
|
||||
<< Op.Val->getNumValues() << ")"
|
||||
<< " " << Op.Val->getOperationName(&DAG);
|
||||
if (isFlagDefiner(Op)) O << "<#";
|
||||
if (isFlagUser(Op)) O << ">#";
|
||||
#endif
|
||||
}
|
||||
|
||||
/// print - Print ordering to specified output stream.
|
||||
///
|
||||
void SimpleSched::print(std::ostream &O) const {
|
||||
#ifndef NDEBUG
|
||||
using namespace std;
|
||||
O << "Ordering\n";
|
||||
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
||||
printSI(O, Ordering[i]);
|
||||
O << "\n";
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/// dump - Print ordering to std::cerr.
|
||||
///
|
||||
void SimpleSched::dump() const {
|
||||
print(std::cerr);
|
||||
}
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
|
||||
/// target node in the graph.
|
||||
void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
|
||||
if (ViewDAGs) SD.viewGraph();
|
||||
BB = SimpleSched(SD, BB).Run();
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user