mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-26 21:32:10 +00:00
Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198238 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
4ba4132d62
commit
e6d2dce7ab
@ -1528,9 +1528,6 @@ static int readOpcodeModifier(struct InternalInstruction* insn) {
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case MODIFIER_OPCODE:
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insn->opcodeModifier = insn->opcode - insn->spec->modifierBase;
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return 0;
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case MODIFIER_MODRM:
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insn->opcodeModifier = insn->modRM - insn->spec->modifierBase;
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return 0;
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}
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}
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@ -526,8 +526,7 @@ struct OperandSpecifier {
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#define MODIFIER_TYPES \
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ENUM_ENTRY(MODIFIER_NONE) \
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ENUM_ENTRY(MODIFIER_OPCODE) \
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ENUM_ENTRY(MODIFIER_MODRM)
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ENUM_ENTRY(MODIFIER_OPCODE)
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#define ENUM_ENTRY(n) n,
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typedef enum {
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@ -218,37 +218,37 @@ defm DIV : FPBinary<fdiv, MRM6m, "div">;
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defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
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}
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class FPST0rInst<bits<8> o, string asm>
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: FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
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class FPrST0Inst<bits<8> o, string asm>
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: FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
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class FPrST0PInst<bits<8> o, string asm>
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: FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
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class FPST0rInst<Format fp, string asm>
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: FPI<0xD8, fp, (outs), (ins RST:$op), asm>;
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class FPrST0Inst<Format fp, string asm>
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: FPI<0xDC, fp, (outs), (ins RST:$op), asm>;
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class FPrST0PInst<Format fp, string asm>
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: FPI<0xDE, fp, (outs), (ins RST:$op), asm>;
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// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
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// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
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// we have to put some 'r's in and take them out of weird places.
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def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
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def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, st(0)}">;
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def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
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def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
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def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
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def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
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def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
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def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
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def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
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def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
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def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, st(0)}">;
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def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
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def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
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def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;
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def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
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def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
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def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
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def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
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def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">;
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def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">;
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def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">;
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def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">;
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def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
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def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">;
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def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">;
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def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
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def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">;
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def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">;
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def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">;
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def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">;
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def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">;
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def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;
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def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">;
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def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">;
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def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
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def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;
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def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">;
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def COMP_FST0r : FPST0rInst <0xD8, "fcomp\t$op">;
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def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
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def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
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// Unary operations.
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multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
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@ -336,22 +336,22 @@ defm CMOVNP : FPCMov<X86_COND_NP>;
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let Predicates = [HasCMov] in {
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// These are not factored because there's no clean way to pass DA/DB.
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def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovb\t{$op, %st(0)|st(0), $op}">, DA;
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def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovbe\t{$op, %st(0)|st(0), $op}">, DA;
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def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
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"fcmove\t{$op, %st(0)|st(0), $op}">, DA;
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def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovu\t{$op, %st(0)|st(0), $op}">, DA;
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def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnb\t{$op, %st(0)|st(0), $op}">, DB;
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def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnbe\t{$op, %st(0)|st(0), $op}">, DB;
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def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovne\t{$op, %st(0)|st(0), $op}">, DB;
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def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
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"fcmovnu\t{$op, %st(0)|st(0), $op}">, DB;
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def CMOVB_F : FPI<0xDA, MRM0r, (outs RST:$op), (ins),
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"fcmovb\t{$op, %st(0)|st(0), $op}">;
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def CMOVBE_F : FPI<0xDA, MRM2r, (outs RST:$op), (ins),
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"fcmovbe\t{$op, %st(0)|st(0), $op}">;
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def CMOVE_F : FPI<0xDA, MRM1r, (outs RST:$op), (ins),
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"fcmove\t{$op, %st(0)|st(0), $op}">;
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def CMOVP_F : FPI<0xDA, MRM3r, (outs RST:$op), (ins),
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"fcmovu\t{$op, %st(0)|st(0), $op}">;
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def CMOVNB_F : FPI<0xDB, MRM0r, (outs RST:$op), (ins),
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"fcmovnb\t{$op, %st(0)|st(0), $op}">;
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def CMOVNBE_F: FPI<0xDB, MRM2r, (outs RST:$op), (ins),
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"fcmovnbe\t{$op, %st(0)|st(0), $op}">;
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def CMOVNE_F : FPI<0xDB, MRM1r, (outs RST:$op), (ins),
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"fcmovne\t{$op, %st(0)|st(0), $op}">;
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def CMOVNP_F : FPI<0xDB, MRM3r, (outs RST:$op), (ins),
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"fcmovnu\t{$op, %st(0)|st(0), $op}">;
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} // Predicates = [HasCMov]
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// Floating point loads & stores.
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@ -492,14 +492,10 @@ def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst),
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// FP Stack manipulation instructions.
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let SchedRW = [WriteMove] in {
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def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op",
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IIC_FLD>, D9;
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def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op",
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IIC_FST>, DD;
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def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op",
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IIC_FST>, DD;
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def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op",
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IIC_FXCH>, D9;
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def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>;
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def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>;
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def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>;
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def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>;
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}
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// Floating point constant loads.
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@ -546,31 +542,26 @@ def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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}
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let Defs = [FPSW], Uses = [ST0] in {
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def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg),
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"fucom\t$reg", IIC_FUCOM>, DD;
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def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg),
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"fucomp\t$reg", IIC_FUCOM>, DD;
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def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>;
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def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>;
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def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
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(outs), (ins),
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"fucompp", IIC_FUCOM>, DA;
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(outs), (ins), "fucompp", IIC_FUCOM>, DA;
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}
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let Defs = [EFLAGS, FPSW], Uses = [ST0] in {
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def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg),
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"fucomi\t$reg", IIC_FUCOMI>, DB;
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def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg),
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"fucompi\t$reg", IIC_FUCOMI>, DF;
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def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg), "fucomi\t$reg", IIC_FUCOMI>;
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def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
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(outs), (ins RST:$reg), "fucompi\t$reg", IIC_FUCOMI>;
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}
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let Defs = [EFLAGS, FPSW] in {
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def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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"fcomi\t$reg", IIC_FCOMI>, DB;
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def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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"fcompi\t$reg", IIC_FCOMI>, DF;
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def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg),
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"fcomi\t$reg", IIC_FCOMI>;
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def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg),
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"fcompi\t$reg", IIC_FCOMI>;
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}
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} // SchedRW
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@ -594,8 +585,8 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
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let SchedRW = [WriteMicrocoded] in {
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let Defs = [FPSW] in
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def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", [], IIC_FNINIT>, DB;
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def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
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"ffree\t$reg", IIC_FFREE>, DD;
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def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
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"ffree\t$reg", IIC_FFREE>;
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// Clear exceptions
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let Defs = [FPSW] in
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@ -17,8 +17,6 @@ void DumbFilter::anchor() { }
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void ModFilter::anchor() { }
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void AddRegEscapeFilter::anchor() { }
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void ExtendedFilter::anchor() { }
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void ExactFilter::anchor() { }
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@ -84,26 +84,6 @@ public:
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}
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};
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/// AddRegEscapeFilter - Some escape opcodes have one of the register operands
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/// added to the ModR/M byte, meaning that a range of eight ModR/M values
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/// maps to a single instruction. Such instructions require the ModR/M byte
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/// to fall between 0xc0 and 0xff.
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class AddRegEscapeFilter : public ModRMFilter {
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virtual void anchor();
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uint8_t ModRM;
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public:
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/// Constructor
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///
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/// \param modRM The value of the ModR/M byte when the register operand
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/// refers to the first register in the register set.
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AddRegEscapeFilter(uint8_t modRM) : ModRM(modRM) {
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}
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bool accepts(uint8_t modRM) const {
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return (modRM >= ModRM && modRM < ModRM + 8);
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}
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};
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/// ExtendedFilter - Extended opcodes are classified based on the value of the
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/// mod field [bits 7-6] and the value of the nnn field [bits 5-3].
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class ExtendedFilter : public ModRMFilter {
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@ -1075,14 +1075,9 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
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case X86Local::DE:
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case X86Local::DF:
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assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
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assert(Form == X86Local::RawFrm);
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opcodeType = ONEBYTE;
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if (Form == X86Local::AddRegFrm) {
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Spec->modifierType = MODIFIER_MODRM;
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Spec->modifierBase = Opcode;
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filter = new AddRegEscapeFilter(Opcode);
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} else {
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filter = new ExactFilter(Opcode);
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}
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filter = new ExactFilter(Opcode);
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opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
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break;
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case X86Local::REP:
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@ -1130,6 +1125,16 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
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switch (Form) {
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default:
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llvm_unreachable("Unhandled escape opcode form");
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case X86Local::MRM0r:
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case X86Local::MRM1r:
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case X86Local::MRM2r:
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case X86Local::MRM3r:
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case X86Local::MRM4r:
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case X86Local::MRM5r:
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case X86Local::MRM6r:
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case X86Local::MRM7r:
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filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
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break;
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case X86Local::MRM0m:
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case X86Local::MRM1m:
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case X86Local::MRM2m:
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@ -1157,31 +1162,22 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
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assert(filter && "Filter not set");
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if (Form == X86Local::AddRegFrm) {
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if(Spec->modifierType != MODIFIER_MODRM) {
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assert(opcodeToSet < 0xf9 &&
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"Not enough room for all ADDREG_FRM operands");
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assert(opcodeToSet < 0xf9 &&
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"Not enough room for all ADDREG_FRM operands");
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uint8_t currentOpcode;
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uint8_t currentOpcode;
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for (currentOpcode = opcodeToSet;
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currentOpcode < opcodeToSet + 8;
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++currentOpcode)
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tables.setTableFields(opcodeType,
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insnContext(),
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currentOpcode,
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*filter,
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UID, Is32Bit, IgnoresVEX_L);
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Spec->modifierType = MODIFIER_OPCODE;
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Spec->modifierBase = opcodeToSet;
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} else {
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// modifierBase was set where MODIFIER_MODRM was set
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for (currentOpcode = opcodeToSet;
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currentOpcode < opcodeToSet + 8;
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++currentOpcode)
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tables.setTableFields(opcodeType,
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insnContext(),
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opcodeToSet,
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currentOpcode,
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*filter,
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UID, Is32Bit, IgnoresVEX_L);
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}
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Spec->modifierType = MODIFIER_OPCODE;
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Spec->modifierBase = opcodeToSet;
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} else {
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||||
tables.setTableFields(opcodeType,
|
||||
insnContext(),
|
||||
@ -1341,6 +1337,7 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString
|
||||
OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
ENCODING("RST", ENCODING_I)
|
||||
ENCODING("GR16", ENCODING_RM)
|
||||
ENCODING("GR32", ENCODING_RM)
|
||||
ENCODING("GR32orGR64", ENCODING_RM)
|
||||
@ -1493,7 +1490,6 @@ OperandEncoding RecognizableInstr::relocationEncodingFromString
|
||||
OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
ENCODING("RST", ENCODING_I)
|
||||
ENCODING("GR32", ENCODING_Rv)
|
||||
ENCODING("GR64", ENCODING_RO)
|
||||
ENCODING("GR16", ENCODING_Rv)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user