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Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and x86.sse2.unpckl.pd intrinsics. These will be lowered into shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51531 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -504,18 +504,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Shuffles.
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// FIXME: Temporary workarounds since 2-wide shuffle is broken.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_movs_d : GCCBuiltin<"__builtin_ia32_movsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_shuf_pd : GCCBuiltin<"__builtin_ia32_shufpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_sse2_unpckh_pd : GCCBuiltin<"__builtin_ia32_unpckhpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_unpckl_pd : GCCBuiltin<"__builtin_ia32_unpcklpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_punpckh_qdq : GCCBuiltin<"__builtin_ia32_punpckhqdq128">,
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Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty,
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llvm_v2i64_ty], [IntrNoMem]>;
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@ -3051,22 +3051,6 @@ def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
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(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
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// FIXME: Temporary workaround since 2-wide shuffle is broken.
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def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
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(v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
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(v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
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Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (memop addr:$src2),imm:$src3),
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(v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
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Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
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(v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (memop addr:$src2)),
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(v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
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(v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (memop addr:$src2)),
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(v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
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(v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (memop addr:$src2)),
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@ -150,7 +150,11 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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return true;
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} else if (Name.compare(5,17,"x86.sse2.loadh.pd",17) == 0 ||
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Name.compare(5,17,"x86.sse2.loadl.pd",17) == 0 ||
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Name.compare(5,16,"x86.sse2.movl.dq",16) == 0) {
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Name.compare(5,16,"x86.sse2.movl.dq",16) == 0 ||
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Name.compare(5,15,"x86.sse2.movs.d",15) == 0 ||
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Name.compare(5,16,"x86.sse2.shuf.pd",16) == 0 ||
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Name.compare(5,18,"x86.sse2.unpckh.pd",18) == 0 ||
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Name.compare(5,18,"x86.sse2.unpckl.pd",18) == 0 ) {
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// Calls to these intrinsics are transformed into ShuffleVector's.
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NewFn = 0;
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return true;
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@ -187,17 +191,28 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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if (!NewFn) {
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bool isLoadH = false, isLoadL = false, isMovL = false;
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bool isMovSD = false, isShufPD = false;
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bool isUnpckhPD = false, isUnpcklPD = false;
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if (strcmp(F->getNameStart(), "llvm.x86.sse2.loadh.pd") == 0)
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isLoadH = true;
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else if (strcmp(F->getNameStart(), "llvm.x86.sse2.loadl.pd") == 0)
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isLoadL = true;
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else if (strcmp(F->getNameStart(), "llvm.x86.sse2.movl.dq") == 0)
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isMovL = true;
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else if (strcmp(F->getNameStart(), "llvm.x86.sse2.movs.d") == 0)
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isMovSD = true;
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else if (strcmp(F->getNameStart(), "llvm.x86.sse2.shuf.pd") == 0)
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isShufPD = true;
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else if (strcmp(F->getNameStart(), "llvm.x86.sse2.unpckh.pd") == 0)
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isUnpckhPD = true;
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else if (strcmp(F->getNameStart(), "llvm.x86.sse2.unpckl.pd") == 0)
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isUnpcklPD = true;
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if (isLoadH || isLoadL || isMovL) {
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if (isLoadH || isLoadL || isMovL || isMovSD || isShufPD ||
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isUnpckhPD || isUnpcklPD) {
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std::vector<Constant*> Idxs;
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Value *Op0 = CI->getOperand(1);
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ShuffleVectorInst *SI;
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ShuffleVectorInst *SI = NULL;
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if (isLoadH || isLoadL) {
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Value *Op1 = UndefValue::get(Op0->getType());
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Value *Addr = new BitCastInst(CI->getOperand(2),
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@ -216,7 +231,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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}
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Value *Mask = ConstantVector::get(Idxs);
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SI = new ShuffleVectorInst(Op0, Op1, Mask, "upgraded.", CI);
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} else {
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} else if (isMovL) {
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Constant *Zero = ConstantInt::get(Type::Int32Ty, 0);
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Idxs.push_back(Zero);
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Idxs.push_back(Zero);
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@ -231,8 +246,31 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, 3));
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Value *Mask = ConstantVector::get(Idxs);
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SI = new ShuffleVectorInst(ZeroV, Op0, Mask, "upgraded.", CI);
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} else if (isMovSD || isUnpckhPD || isUnpcklPD) {
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Value *Op1 = CI->getOperand(2);
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if (isMovSD) {
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, 2));
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, 1));
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} else if (isUnpckhPD) {
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, 1));
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, 3));
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} else {
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, 0));
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, 2));
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}
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Value *Mask = ConstantVector::get(Idxs);
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SI = new ShuffleVectorInst(Op0, Op1, Mask, "upgraded.", CI);
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} else if (isShufPD) {
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Value *Op1 = CI->getOperand(2);
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unsigned MaskVal = cast<ConstantInt>(CI->getOperand(3))->getZExtValue();
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, MaskVal & 1));
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Idxs.push_back(ConstantInt::get(Type::Int32Ty, ((MaskVal >> 1) & 1)+2));
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Value *Mask = ConstantVector::get(Idxs);
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SI = new ShuffleVectorInst(Op0, Op1, Mask, "upgraded.", CI);
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}
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assert(SI && "Unexpected!");
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// Handle any uses of the old CallInst.
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if (!CI->use_empty())
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// Replace all uses of the old call with the new cast which has the
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2
test/Bitcode/sse2_movs_d.ll
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2
test/Bitcode/sse2_movs_d.ll
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@ -0,0 +1,2 @@
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; RUN: llvm-dis < %s.bc | not grep {i32 @llvm\\.movs.d}
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; RUN: llvm-dis < %s.bc | grep shufflevector
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test/Bitcode/sse2_movs_d.ll.bc
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BIN
test/Bitcode/sse2_movs_d.ll.bc
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Binary file not shown.
2
test/Bitcode/sse2_shuf_pd.ll
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2
test/Bitcode/sse2_shuf_pd.ll
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@ -0,0 +1,2 @@
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; RUN: llvm-dis < %s.bc | not grep {i32 @llvm\\.shuf.pd}
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; RUN: llvm-dis < %s.bc | grep shufflevector
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BIN
test/Bitcode/sse2_shuf_pd.ll.bc
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BIN
test/Bitcode/sse2_shuf_pd.ll.bc
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Binary file not shown.
3
test/Bitcode/sse2_unpck_pd.ll
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3
test/Bitcode/sse2_unpck_pd.ll
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@ -0,0 +1,3 @@
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; RUN: llvm-dis < %s.bc | not grep {i32 @llvm\\.unpckh.pd}
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; RUN: llvm-dis < %s.bc | not grep {i32 @llvm\\.unpckl.pd}
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; RUN: llvm-dis < %s.bc | grep shufflevector
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BIN
test/Bitcode/sse2_unpck_pd.ll.bc
Normal file
BIN
test/Bitcode/sse2_unpck_pd.ll.bc
Normal file
Binary file not shown.
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