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Avoid referencing deleted instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-09-19 21:48:07 +00:00
parent 96345186a5
commit e71bff7405
1 changed files with 26 additions and 5 deletions
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31
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@@ -317,7 +317,9 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
/// => /// =>
/// ldmdb rn!, <ra, rb, rc> /// ldmdb rn!, <ra, rb, rc>
static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB, static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) { MachineBasicBlock::iterator MBBI,
bool &Advance,
MachineBasicBlock::iterator &I) {
MachineInstr *MI = MBBI; MachineInstr *MI = MBBI;
unsigned Base = MI->getOperand(0).getReg(); unsigned Base = MI->getOperand(0).getReg();
unsigned Bytes = getLSMultipleTransferSize(MI); unsigned Bytes = getLSMultipleTransferSize(MI);
@@ -358,11 +360,19 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) && if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) { isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true)); MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
if (NextMBBI == I) {
Advance = true;
++I;
}
MBB.erase(NextMBBI); MBB.erase(NextMBBI);
return true; return true;
} else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) && } else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) { isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true)); MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
if (NextMBBI == I) {
Advance = true;
++I;
}
MBB.erase(NextMBBI); MBB.erase(NextMBBI);
return true; return true;
} }
@@ -389,6 +399,10 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
if (Mode == ARM_AM::ia && if (Mode == ARM_AM::ia &&
isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) { isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset)); MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
if (NextMBBI == I) {
Advance = true;
++I;
}
MBB.erase(NextMBBI); MBB.erase(NextMBBI);
} }
return true; return true;
@@ -428,7 +442,9 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
/// register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible: /// register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible:
static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB, static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
const TargetInstrInfo *TII) { const TargetInstrInfo *TII,
bool &Advance,
MachineBasicBlock::iterator &I) {
MachineInstr *MI = MBBI; MachineInstr *MI = MBBI;
unsigned Base = MI->getOperand(1).getReg(); unsigned Base = MI->getOperand(1).getReg();
bool BaseKill = MI->getOperand(1).isKill(); bool BaseKill = MI->getOperand(1).isKill();
@@ -475,9 +491,14 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
DoMerge = true; DoMerge = true;
NewOpc = getPostIndexedLoadStoreOpcode(Opcode); NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
} }
if (DoMerge) if (DoMerge) {
if (NextMBBI == I) {
Advance = true;
++I;
}
MBB.erase(NextMBBI); MBB.erase(NextMBBI);
} }
}
if (!DoMerge) if (!DoMerge)
return false; return false;
@@ -668,7 +689,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
// Try folding preceeding/trailing base inc/dec into the generated // Try folding preceeding/trailing base inc/dec into the generated
// LDM/STM ops. // LDM/STM ops.
for (unsigned i = 0, e = MBBII.size(); i < e; ++i) for (unsigned i = 0, e = MBBII.size(); i < e; ++i)
if (mergeBaseUpdateLSMultiple(MBB, MBBII[i])) if (mergeBaseUpdateLSMultiple(MBB, MBBII[i], Advance, MBBI))
NumMerges++; NumMerges++;
NumMerges += MBBII.size(); NumMerges += MBBII.size();
@@ -676,7 +697,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
// that were not merged to form LDM/STM ops. // that were not merged to form LDM/STM ops.
for (unsigned i = 0; i != NumMemOps; ++i) for (unsigned i = 0; i != NumMemOps; ++i)
if (!MemOps[i].Merged) if (!MemOps[i].Merged)
if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII)) if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
NumMerges++; NumMerges++;
// RS may be pointing to an instruction that's deleted. // RS may be pointing to an instruction that's deleted.