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[mips][microMIPS] Implement CodeGen support for ANDI16 instruction

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Differential Revision: http://reviews.llvm.org/D5797


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221353 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
2014-11-05 15:54:05 +00:00
parent 8cfd4909f0
commit e7ec22de06
3 changed files with 38 additions and 2 deletions
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10
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@@ -31,6 +31,11 @@ def uimm4_andi : Operand<i32> {
let EncoderMethod = "getUImm4AndValue"; let EncoderMethod = "getUImm4AndValue";
} }
def immZExtAndi16 : ImmLeaf<i32,
[{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>; def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>; def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
@@ -509,6 +514,11 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
// MicroMips arbitrary patterns that map to one or more instructions // MicroMips arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
(ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
def : MipsPat<(and GPR32:$src, immZExt16:$imm),
(ANDi_MM GPR32:$src, immZExt16:$imm)>;
def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm), def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
(SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
def : MipsPat<(shl GPR32:$src, immZExt5:$imm), def : MipsPat<(shl GPR32:$src, immZExt5:$imm),

5
lib/Target/Mips/MipsInstrInfo.td
View File

@@ -1105,9 +1105,10 @@ def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xa>; SLTI_FM<0xa>;
def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xb>; SLTI_FM<0xb>;
let AdditionalPredicates = [NotInMicroMips] in {
def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
and>, and>, ADDI_FM<0xc>;
ADDI_FM<0xc>; }
def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
or>, or>,
ADDI_FM<0xd>; ADDI_FM<0xd>;

25
test/CodeGen/Mips/micromips-andi.ll Normal file
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@@ -0,0 +1,25 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@x = global i32 65504, align 4
@y = global i32 60929, align 4
@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
define i32 @main() nounwind {
entry:
%0 = load i32* @x, align 4
%and1 = and i32 %0, 4
%call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
([7 x i8]* @.str, i32 0, i32 0), i32 %and1)
%1 = load i32* @y, align 4
%and2 = and i32 %1, 5
%call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
([7 x i8]* @.str, i32 0, i32 0), i32 %and2)
ret i32 0
}
declare i32 @printf(i8*, ...)
; CHECK: andi16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}
; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}