mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-01 00:33:09 +00:00
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
e05442d508
commit
e86b01c153
@ -68,6 +68,9 @@ public:
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void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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printMemReference(MI, OpNo, O);
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}
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void printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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printMemReference(MI, OpNo, O);
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}
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};
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}
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@ -80,6 +80,10 @@ public:
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O << "XMMWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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void printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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O << "YMMWORD PTR ";
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printMemReference(MI, OpNo, O);
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}
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};
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}
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@ -3147,6 +3147,8 @@ bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
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case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
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case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
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case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
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case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
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case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
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return true;
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}
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return false;
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@ -227,7 +227,7 @@ def f32mem : X86MemOperand<"printf32mem">;
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def f64mem : X86MemOperand<"printf64mem">;
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def f80mem : X86MemOperand<"printf80mem">;
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def f128mem : X86MemOperand<"printf128mem">;
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//def f256mem : X86MemOperand<"printf256mem">;
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def f256mem : X86MemOperand<"printf256mem">;
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// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
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// plain GR64, so that it doesn't potentially require a REX prefix.
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@ -106,6 +106,12 @@ def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
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def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
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def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
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// FIXME: move this to a more appropriate place after all AVX is done.
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def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
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def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
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def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
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def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
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// Like 'store', but always requires vector alignment.
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def alignedstore : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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@ -130,6 +136,16 @@ def alignedloadv4i32 : PatFrag<(ops node:$ptr),
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def alignedloadv2i64 : PatFrag<(ops node:$ptr),
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(v2i64 (alignedload node:$ptr))>;
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// FIXME: move this to a more appropriate place after all AVX is done.
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def alignedloadv8f32 : PatFrag<(ops node:$ptr),
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(v8f32 (alignedload node:$ptr))>;
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def alignedloadv4f64 : PatFrag<(ops node:$ptr),
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(v4f64 (alignedload node:$ptr))>;
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def alignedloadv8i32 : PatFrag<(ops node:$ptr),
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(v8i32 (alignedload node:$ptr))>;
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def alignedloadv4i64 : PatFrag<(ops node:$ptr),
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(v4i64 (alignedload node:$ptr))>;
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// Like 'load', but uses special alignment checks suitable for use in
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// memory operands in most SSE instructions, which are required to
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// be naturally aligned on some targets but not on others. If the subtarget
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@ -583,6 +599,15 @@ defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
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"movups", SSEPackedSingle>, VEX;
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defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
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"movupd", SSEPackedDouble, 0>, OpSize, VEX;
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defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
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"movaps", SSEPackedSingle>, VEX;
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defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
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"movapd", SSEPackedDouble>, OpSize, VEX;
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defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
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"movups", SSEPackedSingle>, VEX;
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defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
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"movupd", SSEPackedDouble, 0>, OpSize, VEX;
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}
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defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
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"movaps", SSEPackedSingle>, TB;
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@ -606,6 +631,18 @@ def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
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def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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[(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
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def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
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"movapd\t{$src, $dst|$dst, $src}",
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[(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
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def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
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"movups\t{$src, $dst|$dst, $src}",
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[(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
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def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
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"movupd\t{$src, $dst|$dst, $src}",
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[(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
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}
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def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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@ -75,7 +75,8 @@ public:
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unsigned OpNum) {
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unsigned SrcReg = MI.getOperand(OpNum).getReg();
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unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
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if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
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if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
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(SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
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SrcRegNum += 8;
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// The registers represented through VEX_VVVV should
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@ -454,6 +455,15 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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break; // No prefix!
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}
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// Set the vector length to 256-bit if YMM0-YMM15 is used
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for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
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if (!MI.getOperand(i).isReg())
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continue;
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unsigned SrcReg = MI.getOperand(i).getReg();
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if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
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VEX_L = 1;
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}
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unsigned NumOps = MI.getNumOperands();
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unsigned CurOp = 0;
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@ -127,21 +127,29 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
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case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
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return RegNo-X86::ST0;
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case X86::XMM0: case X86::XMM8: case X86::MM0:
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case X86::XMM0: case X86::XMM8:
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case X86::YMM0: case X86::YMM8: case X86::MM0:
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return 0;
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case X86::XMM1: case X86::XMM9: case X86::MM1:
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case X86::XMM1: case X86::XMM9:
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case X86::YMM1: case X86::YMM9: case X86::MM1:
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return 1;
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case X86::XMM2: case X86::XMM10: case X86::MM2:
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case X86::XMM2: case X86::XMM10:
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case X86::YMM2: case X86::YMM10: case X86::MM2:
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return 2;
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case X86::XMM3: case X86::XMM11: case X86::MM3:
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case X86::XMM3: case X86::XMM11:
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case X86::YMM3: case X86::YMM11: case X86::MM3:
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return 3;
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case X86::XMM4: case X86::XMM12: case X86::MM4:
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case X86::XMM4: case X86::XMM12:
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case X86::YMM4: case X86::YMM12: case X86::MM4:
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return 4;
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case X86::XMM5: case X86::XMM13: case X86::MM5:
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case X86::XMM5: case X86::XMM13:
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case X86::YMM5: case X86::YMM13: case X86::MM5:
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return 5;
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case X86::XMM6: case X86::XMM14: case X86::MM6:
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case X86::XMM6: case X86::XMM14:
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case X86::YMM6: case X86::YMM14: case X86::MM6:
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return 6;
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case X86::XMM7: case X86::XMM15: case X86::MM7:
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case X86::XMM7: case X86::XMM15:
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case X86::YMM7: case X86::YMM15: case X86::MM7:
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return 7;
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case X86::ES:
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@ -147,7 +147,7 @@ let Namespace = "X86" in {
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def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
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def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
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def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
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// Pseudo Floating Point registers
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def FP0 : Register<"fp0">;
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def FP1 : Register<"fp1">;
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@ -155,7 +155,7 @@ let Namespace = "X86" in {
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def FP3 : Register<"fp3">;
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def FP4 : Register<"fp4">;
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def FP5 : Register<"fp5">;
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def FP6 : Register<"fp6">;
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def FP6 : Register<"fp6">;
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// XMM Registers, used by the various SSE instruction set extensions.
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// The sub_ss and sub_sd subregs are the same registers with another regclass.
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@ -181,7 +181,8 @@ let Namespace = "X86" in {
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}
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// YMM Registers, used by AVX instructions
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let SubRegIndices = [sub_xmm] in {
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// The sub_ss and sub_sd subregs are the same registers with another regclass.
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let CompositeIndices = [(sub_ss), (sub_sd)], SubRegIndices = [sub_xmm] in {
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def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
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def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
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def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
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@ -357,7 +358,7 @@ def GR16 : RegisterClass<"X86", [i16], 16,
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}];
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}
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def GR32 : RegisterClass<"X86", [i32], 32,
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def GR32 : RegisterClass<"X86", [i32], 32,
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[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
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R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
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@ -412,7 +413,7 @@ def GR32 : RegisterClass<"X86", [i32], 32,
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// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
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// RIP isn't really a register and it can't be used anywhere except in an
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// address, but it doesn't cause trouble.
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def GR64 : RegisterClass<"X86", [i64], 64,
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def GR64 : RegisterClass<"X86", [i64], 64,
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[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
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@ -446,7 +447,7 @@ def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> {
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}
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// Debug registers.
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def DEBUG_REG : RegisterClass<"X86", [i32], 32,
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def DEBUG_REG : RegisterClass<"X86", [i32], 32,
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[DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]> {
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}
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@ -787,7 +788,7 @@ def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
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XMM8, XMM9, XMM10, XMM11,
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XMM12, XMM13, XMM14, XMM15]> {
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let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)];
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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@ -803,11 +804,27 @@ def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
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}
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}];
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}
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def VR256 : RegisterClass<"X86", [ v8i32, v4i64, v8f32, v4f64],256,
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def VR256 : RegisterClass<"X86", [v8i32, v4i64, v8f32, v4f64], 256,
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[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
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YMM8, YMM9, YMM10, YMM11,
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YMM12, YMM13, YMM14, YMM15]> {
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let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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VR256Class::iterator
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VR256Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (!Subtarget.is64Bit())
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return end()-8; // Only YMM0 to YMM7 are available in 32-bit mode.
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else
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return end();
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}
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}];
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}
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// Status flags registers.
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@ -12305,3 +12305,52 @@
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// CHECK: vcmpps $31, %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1f]
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vcmptrue_usps %xmm1, %xmm2, %xmm3
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// CHECK: vmovaps (%eax), %ymm2
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// CHECK: encoding: [0xc5,0xfc,0x28,0x10]
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vmovaps (%eax), %ymm2
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// CHECK: vmovaps %ymm1, %ymm2
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// CHECK: encoding: [0xc5,0xfc,0x28,0xd1]
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vmovaps %ymm1, %ymm2
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// CHECK: vmovaps %ymm1, (%eax)
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// CHECK: encoding: [0xc5,0xfc,0x29,0x08]
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vmovaps %ymm1, (%eax)
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// CHECK: vmovapd (%eax), %ymm2
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// CHECK: encoding: [0xc5,0xfd,0x28,0x10]
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vmovapd (%eax), %ymm2
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// CHECK: vmovapd %ymm1, %ymm2
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// CHECK: encoding: [0xc5,0xfd,0x28,0xd1]
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vmovapd %ymm1, %ymm2
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// CHECK: vmovapd %ymm1, (%eax)
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// CHECK: encoding: [0xc5,0xfd,0x29,0x08]
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vmovapd %ymm1, (%eax)
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// CHECK: vmovups (%eax), %ymm2
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// CHECK: encoding: [0xc5,0xfc,0x10,0x10]
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vmovups (%eax), %ymm2
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// CHECK: vmovups %ymm1, %ymm2
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// CHECK: encoding: [0xc5,0xfc,0x10,0xd1]
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vmovups %ymm1, %ymm2
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// CHECK: vmovups %ymm1, (%eax)
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// CHECK: encoding: [0xc5,0xfc,0x11,0x08]
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vmovups %ymm1, (%eax)
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// CHECK: vmovupd (%eax), %ymm2
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// CHECK: encoding: [0xc5,0xfd,0x10,0x10]
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vmovupd (%eax), %ymm2
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// CHECK: vmovupd %ymm1, %ymm2
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// CHECK: encoding: [0xc5,0xfd,0x10,0xd1]
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vmovupd %ymm1, %ymm2
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// CHECK: vmovupd %ymm1, (%eax)
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// CHECK: encoding: [0xc5,0xfd,0x11,0x08]
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vmovupd %ymm1, (%eax)
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@ -2379,3 +2379,52 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: vcmpps $31, %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1f]
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vcmptrue_usps %xmm11, %xmm12, %xmm13
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// CHECK: vmovaps (%rax), %ymm12
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// CHECK: encoding: [0xc5,0x7c,0x28,0x20]
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vmovaps (%rax), %ymm12
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// CHECK: vmovaps %ymm11, %ymm12
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// CHECK: encoding: [0xc4,0x41,0x7c,0x28,0xe3]
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vmovaps %ymm11, %ymm12
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// CHECK: vmovaps %ymm11, (%rax)
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// CHECK: encoding: [0xc5,0x7c,0x29,0x18]
|
||||
vmovaps %ymm11, (%rax)
|
||||
|
||||
// CHECK: vmovapd (%rax), %ymm12
|
||||
// CHECK: encoding: [0xc5,0x7d,0x28,0x20]
|
||||
vmovapd (%rax), %ymm12
|
||||
|
||||
// CHECK: vmovapd %ymm11, %ymm12
|
||||
// CHECK: encoding: [0xc4,0x41,0x7d,0x28,0xe3]
|
||||
vmovapd %ymm11, %ymm12
|
||||
|
||||
// CHECK: vmovapd %ymm11, (%rax)
|
||||
// CHECK: encoding: [0xc5,0x7d,0x29,0x18]
|
||||
vmovapd %ymm11, (%rax)
|
||||
|
||||
// CHECK: vmovups (%rax), %ymm12
|
||||
// CHECK: encoding: [0xc5,0x7c,0x10,0x20]
|
||||
vmovups (%rax), %ymm12
|
||||
|
||||
// CHECK: vmovups %ymm11, %ymm12
|
||||
// CHECK: encoding: [0xc4,0x41,0x7c,0x10,0xe3]
|
||||
vmovups %ymm11, %ymm12
|
||||
|
||||
// CHECK: vmovups %ymm11, (%rax)
|
||||
// CHECK: encoding: [0xc5,0x7c,0x11,0x18]
|
||||
vmovups %ymm11, (%rax)
|
||||
|
||||
// CHECK: vmovupd (%rax), %ymm12
|
||||
// CHECK: encoding: [0xc5,0x7d,0x10,0x20]
|
||||
vmovupd (%rax), %ymm12
|
||||
|
||||
// CHECK: vmovupd %ymm11, %ymm12
|
||||
// CHECK: encoding: [0xc4,0x41,0x7d,0x10,0xe3]
|
||||
vmovupd %ymm11, %ymm12
|
||||
|
||||
// CHECK: vmovupd %ymm11, (%rax)
|
||||
// CHECK: encoding: [0xc5,0x7d,0x11,0x18]
|
||||
vmovupd %ymm11, (%rax)
|
||||
|
||||
|
||||
@ -306,6 +306,7 @@ static int X86TypeFromOpName(LiteralConstantEmitter *type,
|
||||
REG("RFP64");
|
||||
REG("RFP80");
|
||||
REG("VR128");
|
||||
REG("VR256");
|
||||
REG("RST");
|
||||
REG("SEGMENT_REG");
|
||||
REG("DEBUG_REG");
|
||||
@ -339,6 +340,7 @@ static int X86TypeFromOpName(LiteralConstantEmitter *type,
|
||||
MEM("opaque80mem");
|
||||
MEM("i128mem");
|
||||
MEM("f128mem");
|
||||
MEM("f256mem");
|
||||
MEM("opaque512mem");
|
||||
|
||||
// all R, I, R, I
|
||||
|
||||
Loading…
Reference in New Issue
Block a user