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[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.
Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167548 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -247,6 +247,10 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
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}
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setOperationAction(ISD::ADD, MVT::i32, Custom);
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if (HasMips64)
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setOperationAction(ISD::ADD, MVT::i64, Custom);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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@ -914,6 +918,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case ISD::STORE: return LowerSTORE(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
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case ISD::ADD: return LowerADD(Op, DAG);
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}
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return SDValue();
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}
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@ -2541,6 +2546,27 @@ SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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}
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}
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SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
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if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
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|| cast<ConstantSDNode>
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(Op->getOperand(0).getOperand(0))->getZExtValue() != 0
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|| Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
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return SDValue();
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// The pattern
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// (add (frameaddr 0), (frame_to_args_offset))
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// results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
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// (add FrameObject, 0)
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// where FrameObject is a fixed StackObject with offset 0 which points to
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// the old stack pointer.
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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EVT ValTy = Op->getValueType(0);
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int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
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SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
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return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr,
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DAG.getConstant(0, ValTy));
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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@ -272,6 +272,7 @@ namespace llvm {
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization.
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63
test/CodeGen/Mips/eh-dwarf-cfa.ll
Normal file
63
test/CodeGen/Mips/eh-dwarf-cfa.ll
Normal file
@ -0,0 +1,63 @@
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; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-MIPS64
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declare i8* @llvm.eh.dwarf.cfa(i32) nounwind
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declare i8* @llvm.frameaddress(i32) nounwind readnone
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define i8* @f1() nounwind {
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entry:
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%x = alloca [32 x i8], align 1
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%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
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ret i8* %0
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; CHECK: addiu $sp, $sp, -32
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; CHECK: addiu $2, $sp, 32
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}
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define i8* @f2() nounwind {
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entry:
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%x = alloca [65536 x i8], align 1
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%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
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ret i8* %0
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; check stack size (65536 + 8)
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; CHECK: lui $[[R0:[a-z0-9]+]], 65535
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; CHECK: addiu $[[R0]], $[[R0]], -8
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; CHECK: addu $sp, $sp, $[[R0]]
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; check return value ($sp + stack size)
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; CHECK: lui $[[R1:[a-z0-9]+]], 1
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; CHECK: addu $[[R1]], $sp, $[[R1]]
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; CHECK: addiu $2, $[[R1]], 8
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}
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define i32 @f3() nounwind {
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entry:
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%x = alloca [32 x i8], align 1
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%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
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%1 = ptrtoint i8* %0 to i32
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%2 = call i8* @llvm.frameaddress(i32 0)
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%3 = ptrtoint i8* %2 to i32
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%add = add i32 %1, %3
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ret i32 %add
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; CHECK: addiu $sp, $sp, -40
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; check return value ($fp + stack size + $fp)
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; CHECK: addiu $[[R0:[a-z0-9]+]], $fp, 40
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; CHECK: addu $2, $[[R0]], $fp
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}
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define i8* @f4() nounwind {
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entry:
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%x = alloca [32 x i8], align 1
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%0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
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ret i8* %0
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; CHECK-MIPS64: daddiu $sp, $sp, -32
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; CHECK-MIPS64: daddiu $2, $sp, 32
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}
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