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PowerPC: Lowering floor intrinsic for Altivec
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and llvm.nearbyint to Altivec instruction when using 4 single-precision float vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168086 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adhemerval Zanella
parent
71e5ea8860
commit
e95ed2b7af
@ -402,6 +402,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
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addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
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addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
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@ -721,3 +721,13 @@ def : Pat<(v4f32 (sint_to_fp (v4i32 VRRC:$vA))),
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(VCFSX_0 VRRC:$vA)>;
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def : Pat<(v4f32 (uint_to_fp (v4i32 VRRC:$vA))),
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(VCFUX_0 VRRC:$vA)>;
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// Floating-point rounding
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def : Pat<(v4f32 (ffloor (v4f32 VRRC:$vA))),
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(VRFIM VRRC:$vA)>;
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def : Pat<(v4f32 (fceil (v4f32 VRRC:$vA))),
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(VRFIP VRRC:$vA)>;
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def : Pat<(v4f32 (ftrunc (v4f32 VRRC:$vA))),
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(VRFIZ VRRC:$vA)>;
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def : Pat<(v4f32 (fnearbyint (v4f32 VRRC:$vA))),
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(VRFIN VRRC:$vA)>;
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172
test/CodeGen/PowerPC/vec_rounding.ll
Normal file
172
test/CodeGen/PowerPC/vec_rounding.ll
Normal file
@ -0,0 +1,172 @@
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; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
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; Check vector round to single-precision toward -infinity (vrfim)
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; instruction generation using Altivec.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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declare <2 x double> @llvm.floor.v2f64(<2 x double> %p)
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define <2 x double> @floor_v2f64(<2 x double> %p)
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{
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%t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p)
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ret <2 x double> %t
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}
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; CHECK: floor_v2f64:
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; CHECK: bl floor
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; CHECK: bl floor
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declare <4 x double> @llvm.floor.v4f64(<4 x double> %p)
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define <4 x double> @floor_v4f64(<4 x double> %p)
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{
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%t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
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ret <4 x double> %t
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}
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; CHECK: floor_v4f64:
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; CHECK: bl floor
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; CHECK: bl floor
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; CHECK: bl floor
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; CHECK: bl floor
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declare <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
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define <2 x double> @ceil_v2f64(<2 x double> %p)
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{
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%t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
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ret <2 x double> %t
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}
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; CHECK: ceil_v2f64:
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; CHECK: bl ceil
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; CHECK: bl ceil
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declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
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define <4 x double> @ceil_v4f64(<4 x double> %p)
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{
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%t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
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ret <4 x double> %t
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}
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; CHECK: ceil_v4f64:
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; CHECK: bl ceil
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; CHECK: bl ceil
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; CHECK: bl ceil
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; CHECK: bl ceil
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declare <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
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define <2 x double> @trunc_v2f64(<2 x double> %p)
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{
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%t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
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ret <2 x double> %t
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}
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; CHECK: trunc_v2f64:
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; CHECK: bl trunc
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; CHECK: bl trunc
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declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
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define <4 x double> @trunc_v4f64(<4 x double> %p)
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{
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%t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
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ret <4 x double> %t
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}
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; CHECK: trunc_v4f64:
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; CHECK: bl trunc
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; CHECK: bl trunc
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; CHECK: bl trunc
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; CHECK: bl trunc
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declare <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
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define <2 x double> @nearbyint_v2f64(<2 x double> %p)
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{
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%t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
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ret <2 x double> %t
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}
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; CHECK: nearbyint_v2f64:
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; CHECK: bl nearbyint
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; CHECK: bl nearbyint
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declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
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define <4 x double> @nearbyint_v4f64(<4 x double> %p)
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{
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%t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
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ret <4 x double> %t
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}
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; CHECK: nearbyint_v4f64:
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; CHECK: bl nearbyint
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; CHECK: bl nearbyint
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; CHECK: bl nearbyint
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; CHECK: bl nearbyint
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declare <4 x float> @llvm.floor.v4f32(<4 x float> %p)
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define <4 x float> @floor_v4f32(<4 x float> %p)
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{
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%t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
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ret <4 x float> %t
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}
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; CHECK: floor_v4f32:
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; CHECK: vrfim
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declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
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define <8 x float> @floor_v8f32(<8 x float> %p)
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{
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%t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
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ret <8 x float> %t
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}
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; CHECK: floor_v8f32:
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; CHECK: vrfim
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; CHECK: vrfim
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declare <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
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define <4 x float> @ceil_v4f32(<4 x float> %p)
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{
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%t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
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ret <4 x float> %t
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}
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; CHECK: ceil_v4f32:
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; CHECK: vrfip
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declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
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define <8 x float> @ceil_v8f32(<8 x float> %p)
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{
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%t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
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ret <8 x float> %t
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}
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; CHECK: ceil_v8f32:
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; CHECK: vrfip
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; CHECK: vrfip
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declare <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
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define <4 x float> @trunc_v4f32(<4 x float> %p)
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{
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%t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
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ret <4 x float> %t
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}
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; CHECK: trunc_v4f32:
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; CHECK: vrfiz
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declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
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define <8 x float> @trunc_v8f32(<8 x float> %p)
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{
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%t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
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ret <8 x float> %t
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}
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; CHECK: trunc_v8f32:
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; CHECK: vrfiz
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; CHECK: vrfiz
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declare <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
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define <4 x float> @nearbyint_v4f32(<4 x float> %p)
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{
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%t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
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ret <4 x float> %t
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}
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; CHECK: nearbyint_v4f32:
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; CHECK: vrfin
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declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
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define <8 x float> @nearbyint_v8f32(<8 x float> %p)
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{
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%t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
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ret <8 x float> %t
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}
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; CHECK: nearbyint_v8f32:
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; CHECK: vrfin
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; CHECK: vrfin
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