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https://github.com/c64scene-ar/llvm-6502.git
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Allow [ fi#c, imm ] as ARM load / store addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33474 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -122,17 +122,21 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
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if (N.getOpcode() == ISD::ADD)
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if (N.getOpcode() == ISD::ADD)
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getValue();
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int RHSC = (int)RHS->getValue();
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if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits.
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if ((RHSC >= 0 && RHSC < 0x1000) ||
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(RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
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Base = N.getOperand(0);
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, RHSC,
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ARM_AM::no_shift),
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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MVT::i32);
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if (RHSC < 0) {
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return true;
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AddSub = ARM_AM::sub;
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} else if (RHSC < 0 && RHSC > -0x1000) {
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RHSC = - RHSC;
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Base = N.getOperand(0);
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::sub, -RHSC,
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ARM_AM::no_shift),
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ARM_AM::no_shift),
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MVT::i32);
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MVT::i32);
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return true;
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return true;
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@ -245,17 +249,21 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
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// If the RHS is +/- imm8, fold into addr mode.
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// If the RHS is +/- imm8, fold into addr mode.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getValue();
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int RHSC = (int)RHS->getValue();
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if (RHSC >= 0 && RHSC < 256) {
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if ((RHSC >= 0 && RHSC < 256) ||
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(RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
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Base = N.getOperand(0);
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, RHSC),
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MVT::i32);
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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return true;
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if (RHSC < 0) {
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} else if (RHSC < 0 && RHSC > -256) { // note -256 itself isn't allowed.
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AddSub = ARM_AM::sub;
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Base = N.getOperand(0);
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RHSC = - RHSC;
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Offset = CurDAG->getRegister(0, MVT::i32);
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, -RHSC),
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
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MVT::i32);
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return true;
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return true;
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}
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}
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}
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}
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@ -309,14 +317,20 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
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int RHSC = (int)RHS->getValue();
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int RHSC = (int)RHS->getValue();
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if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
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if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
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RHSC >>= 2;
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RHSC >>= 2;
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if (RHSC >= 0 && RHSC < 256) {
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if ((RHSC >= 0 && RHSC < 256) ||
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(RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
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Base = N.getOperand(0);
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Base = N.getOperand(0);
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Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, RHSC),
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if (Base.getOpcode() == ISD::FrameIndex) {
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MVT::i32);
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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return true;
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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} else if (RHSC < 0 && RHSC > -256) { // note -256 itself isn't allowed.
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}
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Base = N.getOperand(0);
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Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::sub,-RHSC),
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
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MVT::i32);
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MVT::i32);
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return true;
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return true;
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}
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}
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