mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Removing old multiply defs and updating references to new versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
ca932f503b
commit
ea204e70fc
lib/Target/Hexagon
@ -900,7 +900,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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}
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// Generate a mpy instruction.
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SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY64, dl, MVT::i64,
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SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
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OP0, OP1);
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ReplaceUses(N, Result);
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return Result;
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@ -1079,7 +1079,7 @@ SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
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}
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// Generate a mpy instruction.
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SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY, dl, MVT::i32,
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SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpy_up, dl, MVT::i32,
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OP0, OP1);
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ReplaceUses(N, Result);
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return Result;
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@ -1112,7 +1112,7 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
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if (isInt<9>(CN->getSExtValue())) {
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SDNode* Result =
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CurDAG->getMachineNode(Hexagon::MPYI_ri, dl,
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CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
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MVT::i32, Mul_0, Val);
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ReplaceUses(N, Result);
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return Result;
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@ -1140,7 +1140,7 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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dyn_cast<ConstantSDNode>(Val.getNode()))
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if (isInt<9>(CN->getSExtValue())) {
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SDNode* Result =
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CurDAG->getMachineNode(Hexagon::MPYI_ri, dl, MVT::i32,
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CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
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Shl2_0, Val);
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ReplaceUses(N, Result);
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return Result;
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@ -2407,152 +2407,6 @@ def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
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(i64 (zext (i32 IntRegs:$src3)))))),
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(M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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// Multiply and use lower result.
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// Rd=+mpyi(Rs,#u8)
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
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def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
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"$dst =+ mpyi($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
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u8ExtPred:$src2))]>;
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// Rd=-mpyi(Rs,#u8)
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def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
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"$dst =- mpyi($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
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u8ImmPred:$src2)))]>;
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// Rd=mpyi(Rs,#m9)
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// s9 is NOT the same as m9 - but it works.. so far.
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// Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
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// depending on the value of m9. See Arch Spec.
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
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CextOpcode = "MPYI", InputType = "imm" in
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def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
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"$dst = mpyi($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
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s9ExtPred:$src2))]>, ImmRegRel;
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// Rd=mpyi(Rs,Rt)
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let CextOpcode = "MPYI", InputType = "reg" in
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def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = mpyi($src1, $src2)",
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[(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>, ImmRegRel;
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// Rx+=mpyi(Rs,#u8)
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let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
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CextOpcode = "MPYI_acc", InputType = "imm" in
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def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
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"$dst += mpyi($src2, #$src3)",
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[(set (i32 IntRegs:$dst),
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(add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
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(i32 IntRegs:$src1)))],
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"$src1 = $dst">, ImmRegRel;
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// Rx-=mpyi(Rs,#u8)
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let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
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def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
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"$dst -= mpyi($src2, #$src3)",
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[(set (i32 IntRegs:$dst),
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(sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
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u8ExtPred:$src3)))],
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"$src1 = $dst">;
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// Multiply and use upper result.
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// Rd=mpy(Rs,Rt.H):<<1:rnd:sat
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// Rd=mpy(Rs,Rt.L):<<1:rnd:sat
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// Rd=mpy(Rs,Rt)
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def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = mpy($src1, $src2)",
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[(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>;
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// Rd=mpy(Rs,Rt):rnd
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// Rd=mpyu(Rs,Rt)
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def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = mpyu($src1, $src2)",
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[(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>;
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// Multiply and use full result.
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// Rdd=mpyu(Rs,Rt)
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def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = mpyu($src1, $src2)",
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[(set (i64 DoubleRegs:$dst),
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(mul (i64 (anyext (i32 IntRegs:$src1))),
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(i64 (anyext (i32 IntRegs:$src2)))))]>;
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// Rdd=mpy(Rs,Rt)
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def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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"$dst = mpy($src1, $src2)",
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[(set (i64 DoubleRegs:$dst),
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(mul (i64 (sext (i32 IntRegs:$src1))),
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(i64 (sext (i32 IntRegs:$src2)))))]>;
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// Multiply and accumulate, use full result.
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// Rxx[+-]=mpy(Rs,Rt)
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// Rxx+=mpy(Rs,Rt)
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def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"$dst += mpy($src2, $src3)",
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[(set (i64 DoubleRegs:$dst),
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(add (mul (i64 (sext (i32 IntRegs:$src2))),
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(i64 (sext (i32 IntRegs:$src3)))),
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(i64 DoubleRegs:$src1)))],
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"$src1 = $dst">;
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// Rxx-=mpy(Rs,Rt)
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def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"$dst -= mpy($src2, $src3)",
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[(set (i64 DoubleRegs:$dst),
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(sub (i64 DoubleRegs:$src1),
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(mul (i64 (sext (i32 IntRegs:$src2))),
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(i64 (sext (i32 IntRegs:$src3))))))],
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"$src1 = $dst">;
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// Rxx[+-]=mpyu(Rs,Rt)
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// Rxx+=mpyu(Rs,Rt)
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def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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IntRegs:$src2, IntRegs:$src3),
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"$dst += mpyu($src2, $src3)",
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[(set (i64 DoubleRegs:$dst),
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(add (mul (i64 (anyext (i32 IntRegs:$src2))),
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(i64 (anyext (i32 IntRegs:$src3)))),
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(i64 DoubleRegs:$src1)))], "$src1 = $dst">;
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// Rxx-=mpyu(Rs,Rt)
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def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"$dst -= mpyu($src2, $src3)",
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[(set (i64 DoubleRegs:$dst),
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(sub (i64 DoubleRegs:$src1),
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(mul (i64 (anyext (i32 IntRegs:$src2))),
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(i64 (anyext (i32 IntRegs:$src3))))))],
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"$src1 = $dst">;
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let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
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InputType = "imm", CextOpcode = "ADD_acc" in
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def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
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IntRegs:$src2, s8Ext:$src3),
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"$dst += add($src2, #$src3)",
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[(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
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s8_16ExtPred:$src3),
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(i32 IntRegs:$src1)))],
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"$src1 = $dst">, ImmRegRel;
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let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
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CextOpcode = "SUB_acc", InputType = "imm" in
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def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
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IntRegs:$src2, s8Ext:$src3),
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"$dst -= add($src2, #$src3)",
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[(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
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(add (i32 IntRegs:$src2),
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s8_16ExtPred:$src3)))],
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"$src1 = $dst">, ImmRegRel;
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//===----------------------------------------------------------------------===//
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// MTYPE/MPYH -
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//===----------------------------------------------------------------------===//
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@ -3892,7 +3746,7 @@ def : Pat<(i64 (zext (i32 IntRegs:$src1))),
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// Multiply 64-bit unsigned and use upper result.
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def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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(i64
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(MPYU64_acc
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(M2_dpmpyuu_acc_s0
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(i64
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(A2_combinew
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(A2_tfrsi 0),
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@ -3901,9 +3755,9 @@ def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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(i64
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(LSRd_ri
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(i64
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(MPYU64_acc
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(M2_dpmpyuu_acc_s0
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(i64
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(MPYU64_acc
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(M2_dpmpyuu_acc_s0
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(i64
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(A2_combinew (A2_tfrsi 0),
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(i32
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@ -3911,7 +3765,8 @@ def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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(i64
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(LSRd_ri
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(i64
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(MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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(M2_dpmpyuu_s0
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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subreg_loreg)))), 32)),
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@ -3927,7 +3782,7 @@ def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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// Multiply 64-bit signed and use upper result.
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def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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(i64
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(MPY64_acc
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(M2_dpmpyss_acc_s0
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(i64
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(A2_combinew (A2_tfrsi 0),
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(i32
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@ -3935,9 +3790,9 @@ def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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(i64
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(LSRd_ri
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(i64
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(MPY64_acc
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(M2_dpmpyss_acc_s0
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(i64
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(MPY64_acc
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(M2_dpmpyss_acc_s0
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(i64
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(A2_combinew (A2_tfrsi 0),
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(i32
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@ -3945,7 +3800,8 @@ def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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(i64
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(LSRd_ri
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(i64
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(MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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(M2_dpmpyuu_s0
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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subreg_loreg)))), 32)),
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@ -4066,7 +3922,7 @@ defm LSL : basic_xtype_reg<"lsl", shl>;
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// Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
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def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
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(i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
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(i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
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//===----------------------------------------------------------------------===//
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// V3 Instructions +
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@ -19,7 +19,7 @@ def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
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(i32
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(EXTRACT_SUBREG
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(i64
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(MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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(M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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subreg_loreg)))),
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@ -31,7 +31,8 @@ def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
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(i32
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(EXTRACT_SUBREG
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(i64
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(MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
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(M2_dpmpyuu_s0
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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subreg_loreg)))), subreg_loreg))))>;
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