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Code Issues Projects Releases Wiki Activity

Remove a bunch more SparcV9 specific stuff

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28093 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-05-04 01:15:02 +00:00
parent 34fb2cad46
commit ea50fabfd4
14 changed files with 29 additions and 147 deletions
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82
include/llvm/CodeGen/MachineInstr.h
View File

@ -58,9 +58,6 @@ typedef short MachineOpCode;
// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
// MachineInstr* minstr will point to the instruction that computes reg.
//
// - %sp will be of virtual register type MO_MachineReg.
// The field regNum identifies the machine register.
//
// - NumElements will be of virtual register type MO_VirtualReg.
// The field Value* value identifies the value.
//
@ -75,7 +72,6 @@ private:
enum {
DEFFLAG = 0x01, // this is a def of the operand
USEFLAG = 0x02, // this is a use of the operand
PCRELATIVE = 0x40 // Operand is relative to PC, not a global address
};
public:
@ -93,7 +89,6 @@ public:
enum MachineOperandType {
MO_VirtualRegister, // virtual register for *value
MO_MachineRegister, // pre-assigned machine register `regNum'
MO_SignExtendedImmed,
MO_UnextendedImmed,
MO_MachineBasicBlock, // MachineBasicBlock reference
@ -152,18 +147,9 @@ private:
extra.regNum = Reg;
}
MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
bool isPCRelative = false)
: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
assert(OpTy != MachineOperand::MO_GlobalAddress);
zeroContents();
contents.value = V;
extra.regNum = -1;
}
MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy,
bool isPCRelative = false, int Offset = 0)
: flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
int Offset = 0)
: flags(UseTy), opType(OpTy) {
assert(OpTy == MachineOperand::MO_GlobalAddress);
zeroContents ();
contents.value = (Value*)V;
@ -177,8 +163,8 @@ private:
extra.regNum = -1;
}
MachineOperand(const char *SymName, bool isPCRelative, int Offset)
: flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol) {
MachineOperand(const char *SymName, int Offset)
: flags(0), opType(MO_ExternalSymbol) {
zeroContents ();
contents.SymbolName = SymName;
extra.offset = Offset;
@ -192,7 +178,6 @@ public:
extra = M.extra;
}
~MachineOperand() {}
const MachineOperand &operator=(const MachineOperand &MO) {
@ -218,7 +203,7 @@ public:
/// Note: The sparc backend should not use this method.
///
bool isRegister() const {
return opType == MO_MachineRegister || opType == MO_VirtualRegister;
return opType == MO_VirtualRegister;
}
/// Accessors that tell you what kind of MachineOperand you're looking at.
@ -247,10 +232,6 @@ public:
assert(opType == MO_VirtualRegister && "Wrong MachineOperand accessor");
return contents.value;
}
int getMachineRegNum() const {
assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor");
return extra.regNum;
}
int64_t getImmedValue() const {
assert(isImmediate() && "Wrong MachineOperand accessor");
return contents.immedVal;
@ -301,8 +282,7 @@ public:
/// allocated to this operand.
///
bool hasAllocatedReg() const {
return (extra.regNum >= 0 &&
(opType == MO_VirtualRegister || opType == MO_MachineRegister));
return extra.regNum >= 0 && opType == MO_VirtualRegister;
}
/// getReg - Returns the register number. It is a runtime error to call this
@ -445,28 +425,6 @@ public:
// Accessors to add operands when building up machine instructions
//
/// addRegOperand - Add a MO_VirtualRegister operand to the end of the
/// operands list...
///
void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
MachineOperand(V, MachineOperand::MO_VirtualRegister,
!isDef ? MachineOperand::Use :
(isDefAndUse ? MachineOperand::UseAndDef :
MachineOperand::Def)));
}
void addRegOperand(Value *V,
MachineOperand::UseType UTy = MachineOperand::Use,
bool isPCRelative = false) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
UTy, isPCRelative));
}
/// addRegOperand - Add a symbolic virtual register reference...
///
void addRegOperand(int reg, bool isDef) {
@ -487,26 +445,6 @@ public:
MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy));
}
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
///
void addMachineRegOperand(int reg, bool isDef) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
MachineOperand(reg, MachineOperand::MO_MachineRegister,
isDef ? MachineOperand::Def : MachineOperand::Use));
}
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
///
void addMachineRegOperand(int reg,
MachineOperand::UseType UTy = MachineOperand::Use) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy));
}
/// addZeroExtImmOperand - Add a zero extended constant argument to the
/// machine instruction.
///
@ -569,18 +507,18 @@ public:
operands.push_back(MachineOperand(I, MachineOperand::MO_JumpTableIndex));
}
void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative, int Offset) {
void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
MachineOperand(GV, MachineOperand::MO_GlobalAddress,
MachineOperand::Use, isPCRelative, Offset));
MachineOperand::Use, Offset));
}
/// addExternalSymbolOperand - Add an external symbol operand to this instr
///
void addExternalSymbolOperand(const char *SymName, bool isPCRelative) {
operands.push_back(MachineOperand(SymName, isPCRelative, 0));
void addExternalSymbolOperand(const char *SymName) {
operands.push_back(MachineOperand(SymName, 0));
}
//===--------------------------------------------------------------------===//

24
include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -46,22 +46,6 @@ public:
return *this;
}
/// addReg - Add an LLVM value that is to be used as a register...
///
const MachineInstrBuilder &addReg(
Value *V,
MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addRegOperand(V, Ty);
return *this;
}
/// addRegDef - Add an LLVM value that is to be defined as a register... this
/// is the same as addReg(V, MachineOperand::Def).
///
const MachineInstrBuilder &addRegDef(Value *V) const {
return addReg(V, MachineOperand::Def);
}
/// addImm - Add a new immediate operand.
///
const MachineInstrBuilder &addImm(int Val) const {
@ -112,15 +96,13 @@ public:
}
const MachineInstrBuilder &addGlobalAddress(GlobalValue *GV,
bool isPCRelative = false,
int Offset = 0) const {
MI->addGlobalAddressOperand(GV, isPCRelative, Offset);
MI->addGlobalAddressOperand(GV, Offset);
return *this;
}
const MachineInstrBuilder &addExternalSymbol(const char *FnName,
bool isPCRelative = false) const{
MI->addExternalSymbolOperand(FnName, isPCRelative);
const MachineInstrBuilder &addExternalSymbol(const char *FnName) const{
MI->addExternalSymbolOperand(FnName);
return *this;
}
};

8
lib/CodeGen/MachineInstr.cpp
View File

@ -141,7 +141,7 @@ MachineInstr::SetMachineOperandConst(unsigned i,
void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
assert(i < getNumOperands()); // must be explicit op
operands[i].opType = MachineOperand::MO_MachineRegister;
operands[i].opType = MachineOperand::MO_VirtualRegister;
operands[i].contents.value = NULL;
operands[i].extra.regNum = regNum;
}
@ -187,9 +187,6 @@ static void print(const MachineOperand &MO, std::ostream &OS,
if (MO.hasAllocatedReg())
OutputReg(OS, MO.getReg(), MRI);
break;
case MachineOperand::MO_MachineRegister:
OutputReg(OS, MO.getMachineRegNum(), MRI);
break;
case MachineOperand::MO_SignExtendedImmed:
OS << (long)MO.getImmedValue();
break;
@ -297,9 +294,6 @@ std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
OutputValue(OS, MO.getVRegValue());
}
break;
case MachineOperand::MO_MachineRegister:
OutputReg(OS, MO.getMachineRegNum());
break;
case MachineOperand::MO_SignExtendedImmed:
OS << (long)MO.getImmedValue();
break;

10
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -110,7 +110,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
MI->addRegOperand(R->getReg(), MachineOperand::Use);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
} else if (BasicBlockSDNode *BB =
dyn_cast<BasicBlockSDNode>(Op)) {
MI->addMachineBasicBlockOperand(BB->getBasicBlock());
@ -143,7 +143,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
MI->addConstantPoolIndexOperand(Idx, Offset);
} else if (ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Op)) {
MI->addExternalSymbolOperand(ES->getSymbol(), false);
MI->addExternalSymbolOperand(ES->getSymbol());
} else {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag &&
@ -296,7 +296,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
// Add the asm string as an external symbol operand.
const char *AsmStr =
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
MI->addExternalSymbolOperand(AsmStr, false);
MI->addExternalSymbolOperand(AsmStr);
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
@ -311,13 +311,13 @@ void ScheduleDAG::EmitNode(SDNode *Node,
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addMachineRegOperand(Reg, MachineOperand::Use);
MI->addRegOperand(Reg, MachineOperand::Use);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addMachineRegOperand(Reg, MachineOperand::Def);
MI->addRegOperand(Reg, MachineOperand::Def);
}
break;
case 3: { // Immediate.

8
lib/Target/Alpha/AlphaAsmPrinter.cpp
View File

@ -77,7 +77,7 @@ FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
{
const MachineOperand &MO = MI->getOperand(opNum);
if (MO.getType() == MachineOperand::MO_MachineRegister) {
if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
@ -94,12 +94,6 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (Value *V = MO.getVRegValueOrNull()) {
O << "<" << V->getName() << ">";
return;
}
// FALLTHROUGH
case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;

3
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -263,7 +263,8 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
.addReg(Alpha::R29).addImm(curgpdist);
//evil const_cast until MO stuff setup to handle const
BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast<Function*>(MF.getFunction()), true);
BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
.addGlobalAddress(const_cast<Function*>(MF.getFunction()));
// Get the number of bytes to allocate from the FrameInfo
long NumBytes = MFI->getStackSize();

8
lib/Target/IA64/IA64AsmPrinter.cpp
View File

@ -66,7 +66,7 @@ namespace {
// This method is used by the tablegen'erated instruction printer.
void printOperand(const MachineInstr *MI, unsigned OpNo){
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_MachineRegister) {
if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
//XXX Bug Workaround: See note in Printer::doInitialization about %.
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
@ -174,12 +174,6 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (Value *V = MO.getVRegValueOrNull()) {
O << "<" << V->getName() << ">";
return;
}
// FALLTHROUGH
case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;

9
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -86,7 +86,7 @@ namespace {
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_MachineRegister) {
if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
@ -353,13 +353,6 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) {
int new_symbol;
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (Value *V = MO.getVRegValueOrNull()) {
O << "<" << V->getName() << ">";
return;
}
// FALLTHROUGH
case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;

9
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -147,12 +147,6 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
}
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (Value *V = MO.getVRegValueOrNull()) {
O << "<" << V->getName() << ">";
break;
}
// FALLTHROUGH
case MachineOperand::MO_MachineRegister:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
else
@ -195,8 +189,7 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
if ((OpTy == MachineOperand::MO_VirtualRegister ||
OpTy == MachineOperand::MO_MachineRegister) &&
if (OpTy == MachineOperand::MO_VirtualRegister &&
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
if ((OpTy == MachineOperand::MO_SignExtendedImmed ||

1
lib/Target/X86/X86ATTAsmPrinter.cpp
View File

@ -109,7 +109,6 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_MachineRegister:
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
O << '%';

2
lib/Target/X86/X86InstrBuilder.h
View File

@ -93,7 +93,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
assert (0);
MIB.addZImm(AM.Scale).addReg(AM.IndexReg);
if (AM.GV)
return MIB.addGlobalAddress(AM.GV, false, AM.Disp);
return MIB.addGlobalAddress(AM.GV, AM.Disp);
else
return MIB.addSImm(AM.Disp);
}

6
lib/Target/X86/X86IntelAsmPrinter.cpp
View File

@ -115,12 +115,6 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (Value *V = MO.getVRegValueOrNull()) {
O << "<" << V->getName() << ">";
return;
}
// FALLTHROUGH
case MachineOperand::MO_MachineRegister:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << RI.get(MO.getReg()).Name;
else

4
lib/Target/X86/X86IntelAsmPrinter.h
View File

@ -37,8 +37,8 @@ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
void printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier = 0) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.getType() == MachineOperand::MO_MachineRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else {
printOp(MO, Modifier);

2
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -150,7 +150,7 @@ static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
else if (MI->getOperand(1).isGlobalAddress())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addGlobalAddress(MI->getOperand(1).getGlobal(),
false, MI->getOperand(1).getOffset());
MI->getOperand(1).getOffset());
else if (MI->getOperand(1).isJumpTableIndex())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addJumpTableIndex(MI->getOperand(1).getJumpTableIndex());