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Remove the ZERO_EXTEND_INREG node which is redundant with AND

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21263 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-04-13 02:36:41 +00:00
parent db81ebab89
commit ea57610689
1 changed files with 5 additions and 7 deletions
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12
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -141,13 +141,12 @@ namespace ISD {
SINT_TO_FP,
UINT_TO_FP,
// SIGN_EXTEND_INREG/ZERO_EXTEND_INREG - These operators atomically performs
// a SHL/(SRA|SHL) pair to (sign|zero) extend a small value in a large
// integer register (e.g. sign extending the low 8 bits of a 32-bit register
// to fill the top 24 bits with the 7th bit). The size of the smaller type
// is indicated by the ExtraValueType in the MVTSDNode for the operator.
// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
// sign extend a small value in a large integer register (e.g. sign
// extending the low 8 bits of a 32-bit register to fill the top 24 bits
// with the 7th bit). The size of the smaller type is indicated by the
// ExtraValueType in the MVTSDNode for the operator.
SIGN_EXTEND_INREG,
ZERO_EXTEND_INREG,
// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
// integer.
@ -809,7 +808,6 @@ public:
static bool classof(const SDNode *N) {
return
N->getOpcode() == ISD::SIGN_EXTEND_INREG ||
N->getOpcode() == ISD::ZERO_EXTEND_INREG ||
N->getOpcode() == ISD::FP_ROUND_INREG ||
N->getOpcode() == ISD::EXTLOAD ||
N->getOpcode() == ISD::SEXTLOAD ||