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Tighten test case a bit.

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Ideally, we would match an S-register to its containing D-register, but that
requires arithmetic (divide by 2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129756 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-04-19 06:14:45 +00:00
parent 832e494359
commit ea70a06fa7
1 changed files with 2 additions and 1 deletions
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3
test/CodeGen/ARM/fcopysign.ll
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@ -45,7 +45,8 @@ define i32 @test4() ssp {
entry: entry:
; SOFT: test4: ; SOFT: test4:
; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00 ; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
; SOFT: vcvt.f32.f64 {{s[0-9]+}}, [[REG4]] ; This S-reg must be the first sub-reg of the last D-reg on vbsl.
; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]]
; SOFT: vshr.u64 [[REG4]], [[REG4]], #32 ; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000 ; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}} ; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}