6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-14 00:32:55 +00:00
Code Issues Projects Releases Wiki Activity

[AArch64] Refactor NEON floating-point Max/Min/Maxnm/Minnm across vector AArch64

Browse Source 
intrinsics to use f32 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197090 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2013-12-11 23:21:25 +00:00
parent 598ee5a3e7
commit eb1bac0afa
3 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
include/llvm/IR/IntrinsicsAArch64.td
View File

@ -98,10 +98,14 @@ def int_aarch64_neon_umaxv : Neon_Across_Intrinsic;
def int_aarch64_neon_sminv : Neon_Across_Intrinsic; def int_aarch64_neon_sminv : Neon_Across_Intrinsic;
def int_aarch64_neon_uminv : Neon_Across_Intrinsic; def int_aarch64_neon_uminv : Neon_Across_Intrinsic;
def int_aarch64_neon_vaddv : Neon_Across_Intrinsic; def int_aarch64_neon_vaddv : Neon_Across_Intrinsic;
def int_aarch64_neon_vmaxv : Neon_Across_Intrinsic; def int_aarch64_neon_vmaxv :
def int_aarch64_neon_vminv : Neon_Across_Intrinsic; Intrinsic<[llvm_float_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_aarch64_neon_vmaxnmv : Neon_Across_Intrinsic; def int_aarch64_neon_vminv :
def int_aarch64_neon_vminnmv : Neon_Across_Intrinsic; Intrinsic<[llvm_float_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_aarch64_neon_vmaxnmv :
Intrinsic<[llvm_float_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_aarch64_neon_vminnmv :
Intrinsic<[llvm_float_ty], [llvm_v4f32_ty], [IntrNoMem]>;
// Vector Table Lookup. // Vector Table Lookup.
def int_aarch64_neon_vtbl1 : def int_aarch64_neon_vtbl1 :

4
lib/Target/AArch64/AArch64InstrNEON.td
View File

@ -2385,8 +2385,8 @@ multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
def _1s4s: NeonI_2VAcross<0b1, u, size, opcode, def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
(outs FPR32:$Rd), (ins VPR128:$Rn), (outs FPR32:$Rd), (ins VPR128:$Rn),
asmop # "\t$Rd, $Rn.4s", asmop # "\t$Rd, $Rn.4s",
[(set (v1f32 FPR32:$Rd), [(set (f32 FPR32:$Rd),
(v1f32 (opnode (v4f32 VPR128:$Rn))))], (f32 (opnode (v4f32 VPR128:$Rn))))],
NoItinerary>; NoItinerary>;
} }

20
test/CodeGen/AArch64/neon-across.ll
View File

@ -1,12 +1,12 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
declare <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v4f32(<4 x float>) declare float @llvm.aarch64.neon.vminnmv(<4 x float>)
declare <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v4f32(<4 x float>) declare float @llvm.aarch64.neon.vmaxnmv(<4 x float>)
declare <1 x float> @llvm.aarch64.neon.vminv.v1f32.v4f32(<4 x float>) declare float @llvm.aarch64.neon.vminv(<4 x float>)
declare <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v4f32(<4 x float>) declare float @llvm.aarch64.neon.vmaxv(<4 x float>)
declare <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v4i32(<4 x i32>) declare <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v4i32(<4 x i32>)
@ -442,8 +442,7 @@ define float @test_vmaxvq_f32(<4 x float> %a) {
; CHECK: test_vmaxvq_f32: ; CHECK: test_vmaxvq_f32:
; CHECK: fmaxv s{{[0-9]+}}, {{v[0-9]+}}.4s ; CHECK: fmaxv s{{[0-9]+}}, {{v[0-9]+}}.4s
entry: entry:
%vmaxv.i = tail call <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v4f32(<4 x float> %a) %0 = call float @llvm.aarch64.neon.vmaxv(<4 x float> %a)
%0 = extractelement <1 x float> %vmaxv.i, i32 0
ret float %0 ret float %0
} }
@ -451,8 +450,7 @@ define float @test_vminvq_f32(<4 x float> %a) {
; CHECK: test_vminvq_f32: ; CHECK: test_vminvq_f32:
; CHECK: fminv s{{[0-9]+}}, {{v[0-9]+}}.4s ; CHECK: fminv s{{[0-9]+}}, {{v[0-9]+}}.4s
entry: entry:
%vminv.i = tail call <1 x float> @llvm.aarch64.neon.vminv.v1f32.v4f32(<4 x float> %a) %0 = call float @llvm.aarch64.neon.vminv(<4 x float> %a)
%0 = extractelement <1 x float> %vminv.i, i32 0
ret float %0 ret float %0
} }
@ -460,8 +458,7 @@ define float @test_vmaxnmvq_f32(<4 x float> %a) {
; CHECK: test_vmaxnmvq_f32: ; CHECK: test_vmaxnmvq_f32:
; CHECK: fmaxnmv s{{[0-9]+}}, {{v[0-9]+}}.4s ; CHECK: fmaxnmv s{{[0-9]+}}, {{v[0-9]+}}.4s
entry: entry:
%vmaxnmv.i = tail call <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v4f32(<4 x float> %a) %0 = call float @llvm.aarch64.neon.vmaxnmv(<4 x float> %a)
%0 = extractelement <1 x float> %vmaxnmv.i, i32 0
ret float %0 ret float %0
} }
@ -469,8 +466,7 @@ define float @test_vminnmvq_f32(<4 x float> %a) {
; CHECK: test_vminnmvq_f32: ; CHECK: test_vminnmvq_f32:
; CHECK: fminnmv s{{[0-9]+}}, {{v[0-9]+}}.4s ; CHECK: fminnmv s{{[0-9]+}}, {{v[0-9]+}}.4s
entry: entry:
%vminnmv.i = tail call <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v4f32(<4 x float> %a) %0 = call float @llvm.aarch64.neon.vminnmv(<4 x float> %a)
%0 = extractelement <1 x float> %vminnmv.i, i32 0
ret float %0 ret float %0
} }