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R600/SI: Remove dead code and add missing tests.

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This probably was killed by some generic DAGCombiner
improvements in checking the TargetBooleanContents instead
of just 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213471 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-07-20 06:11:02 +00:00
parent 06bc9c4663
commit eb957bfe32
3 changed files with 39 additions and 24 deletions
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14
lib/Target/R600/SIISelLowering.cpp
View File

@ -1241,20 +1241,6 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
switch (N->getOpcode()) {
default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
case ISD::SELECT_CC: {
ConstantSDNode *True, *False;
// i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
&& (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
&& True->isAllOnesValue()
&& False->isNullValue()
&& VT == MVT::i1) {
return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
N->getOperand(1), N->getOperand(4));
}
break;
}
case ISD::SETCC: {
SDValue Arg0 = N->getOperand(0);
SDValue Arg1 = N->getOperand(1);

34
test/CodeGen/R600/selectcc-opt.ll
View File

@ -1,8 +1,10 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; CHECK: @test_a
; CHECK-NOT: CND
; CHECK: SET{{[NEQGTL]+}}_DX10
; FUNC-LABEL: @test_a
; EG-NOT: CND
; EG: SET{{[NEQGTL]+}}_DX10
define void @test_a(i32 addrspace(1)* %out, float %in) {
entry:
@ -28,10 +30,10 @@ ENDIF:
; Same as test_a, but the branch labels are swapped to produce the inverse cc
; for the icmp instruction
; CHECK: @test_b
; CHECK: SET{{[GTEQN]+}}_DX10
; CHECK-NEXT: PRED_
; CHECK-NEXT: ALU clause starting
; EG-LABEL: @test_b
; EG: SET{{[GTEQN]+}}_DX10
; EG-NEXT: PRED_
; EG-NEXT: ALU clause starting
define void @test_b(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp olt float %in, 0.0
@ -54,8 +56,8 @@ ENDIF:
}
; Test a CND*_INT instruction with float true/false values
; CHECK: @test_c
; CHECK: CND{{[GTE]+}}_INT
; EG-LABEL: @test_c
; EG: CND{{[GTE]+}}_INT
define void @test_c(float addrspace(1)* %out, i32 %in) {
entry:
%0 = icmp sgt i32 %in, 0
@ -63,3 +65,15 @@ entry:
store float %1, float addrspace(1)* %out
ret void
}
; FUNC-LABEL: @selectcc_bool
; SI: V_CMP_NE_I32
; SI-NEXT: V_CNDMASK_B32_e64
; SI-NOT: CMP
; SI-NOT: CNDMASK
define void @selectcc_bool(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b
%ext = select i1 %icmp0, i32 -1, i32 0
store i32 %ext, i32 addrspace(1)* %out
ret void
}

15
test/CodeGen/R600/setcc-opt.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; SI-LABEL: @sext_bool_icmp_ne
; SI: V_CMP_NE_I32
; SI-NEXT: V_CNDMASK_B32
; SI-NOT: V_CMP_NE_I32
; SI-NOT: V_CNDMASK_B32
; SI: S_ENDPGM
define void @sext_bool_icmp_ne(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%icmp0 = icmp ne i32 %a, %b
%ext = sext i1 %icmp0 to i32
%icmp1 = icmp ne i32 %ext, 0
store i1 %icmp1, i1 addrspace(1)* %out
ret void
}