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Pass an explicit operand number to addLiveIns.

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Not all instructions define a virtual register in their first operand.
Specifically, INLINEASM has a different format.

<rdar://problem/12472811>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2012-10-11 16:46:07 +00:00
parent a867f37897
commit ebba49395c
3 changed files with 40 additions and 8 deletions
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14
lib/CodeGen/MachineTraceMetrics.cpp
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@@ -850,14 +850,14 @@ static bool pushDepHeight(const DataDep &Dep,
return false; return false;
} }
/// Assuming that DefMI was used by Trace.back(), add it to the live-in lists /// Assuming that the virtual register defined by DefMI:DefOp was used by
/// of all the blocks in Trace. Stop when reaching the block that contains /// Trace.back(), add it to the live-in lists of all the blocks in Trace. Stop
/// DefMI. /// when reaching the block that contains DefMI.
void MachineTraceMetrics::Ensemble:: void MachineTraceMetrics::Ensemble::
addLiveIns(const MachineInstr *DefMI, addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
ArrayRef<const MachineBasicBlock*> Trace) { ArrayRef<const MachineBasicBlock*> Trace) {
assert(!Trace.empty() && "Trace should contain at least one block"); assert(!Trace.empty() && "Trace should contain at least one block");
unsigned Reg = DefMI->getOperand(0).getReg(); unsigned Reg = DefMI->getOperand(DefOp).getReg();
assert(TargetRegisterInfo::isVirtualRegister(Reg)); assert(TargetRegisterInfo::isVirtualRegister(Reg));
const MachineBasicBlock *DefMBB = DefMI->getParent(); const MachineBasicBlock *DefMBB = DefMI->getParent();
@@ -950,7 +950,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
DEBUG(dbgs() << "pred\t" << Height << '\t' << *PHI); DEBUG(dbgs() << "pred\t" << Height << '\t' << *PHI);
if (pushDepHeight(Deps.front(), PHI, Height, if (pushDepHeight(Deps.front(), PHI, Height,
Heights, MTM.SchedModel, MTM.TII)) Heights, MTM.SchedModel, MTM.TII))
addLiveIns(Deps.front().DefMI, Stack); addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack);
} }
} }
} }
@@ -983,7 +983,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
// Update the required height of any virtual registers read by MI. // Update the required height of any virtual registers read by MI.
for (unsigned i = 0, e = Deps.size(); i != e; ++i) for (unsigned i = 0, e = Deps.size(); i != e; ++i)
if (pushDepHeight(Deps[i], MI, Cycle, Heights, MTM.SchedModel, MTM.TII)) if (pushDepHeight(Deps[i], MI, Cycle, Heights, MTM.SchedModel, MTM.TII))
addLiveIns(Deps[i].DefMI, Stack); addLiveIns(Deps[i].DefMI, Deps[i].DefOp, Stack);
InstrCycles &MICycles = Cycles[MI]; InstrCycles &MICycles = Cycles[MI];
MICycles.Height = Cycle; MICycles.Height = Cycle;

2
lib/CodeGen/MachineTraceMetrics.h
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@@ -279,7 +279,7 @@ public:
unsigned computeCrossBlockCriticalPath(const TraceBlockInfo&); unsigned computeCrossBlockCriticalPath(const TraceBlockInfo&);
void computeInstrDepths(const MachineBasicBlock*); void computeInstrDepths(const MachineBasicBlock*);
void computeInstrHeights(const MachineBasicBlock*); void computeInstrHeights(const MachineBasicBlock*);
void addLiveIns(const MachineInstr *DefMI, void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
ArrayRef<const MachineBasicBlock*> Trace); ArrayRef<const MachineBasicBlock*> Trace);
protected: protected:

32
test/CodeGen/X86/early-ifcvt-crash.ll Normal file
View File

@@ -0,0 +1,32 @@
; RUN: llc < %s -x86-early-ifcvt -verify-machineinstrs
; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt -verify-machineinstrs
;
; Run these tests with and without -stress-early-ifcvt to exercise heuristics.
;
target triple = "x86_64-apple-macosx10.8.0"
; MachineTraceMetrics::Ensemble::addLiveIns crashes because the first operand
; on an inline asm instruction is not a vreg def.
; <rdar://problem/12472811>
define void @f1() nounwind {
entry:
br i1 undef, label %if.then6.i, label %if.end.i
if.then6.i:
br label %if.end.i
if.end.i:
br i1 undef, label %if.end25.i, label %if.else17.i
if.else17.i:
%shl24.i = shl i32 undef, undef
br label %if.end25.i
if.end25.i:
%storemerge31.i = phi i32 [ %shl24.i, %if.else17.i ], [ 0, %if.end.i ]
store i32 %storemerge31.i, i32* undef, align 4
%0 = tail call i32 asm sideeffect "", "=r,r,i,i"(i32 undef, i32 15, i32 1) nounwind
%conv = trunc i32 %0 to i8
store i8 %conv, i8* undef, align 1
unreachable
}