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more condition codes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30567 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -87,7 +87,14 @@ namespace llvm {
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/// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC
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static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code!");
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default:
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std::cerr << "CC = " << CC << "\n";
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assert(0 && "Unknown condition code!");
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case ISD::SETUGT: return ARMCC::HI;
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case ISD::SETULE: return ARMCC::LS;
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case ISD::SETLE: return ARMCC::LE;
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case ISD::SETLT: return ARMCC::LT;
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case ISD::SETGT: return ARMCC::GT;
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case ISD::SETNE: return ARMCC::NE;
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case ISD::SETEQ: return ARMCC::EQ;
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case ISD::SETGE: return ARMCC::GE;
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@ -1,8 +1,49 @@
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; RUN: llvm-as < %s | llc -march=arm
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; RUN: llvm-as < %s | llc -march=arm &&
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; RUN: llvm-as < %s | llc -march=arm | grep moveq | wc -l | grep 1 &&
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; RUN: llvm-as < %s | llc -march=arm | grep movgt | wc -l | grep 1 &&
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; RUN: llvm-as < %s | llc -march=arm | grep movlt | wc -l | grep 1 &&
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; RUN: llvm-as < %s | llc -march=arm | grep movle | wc -l | grep 1 &&
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; RUN: llvm-as < %s | llc -march=arm | grep movls | wc -l | grep 1 &&
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; RUN: llvm-as < %s | llc -march=arm | grep movhi | wc -l | grep 1
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int %f(int %a) {
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int %f1(int %a) {
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entry:
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%tmp = seteq int %a, 4 ; <bool> [#uses=1]
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%tmp1 = select bool %tmp, int 2, int 3
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ret int %tmp1
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}
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int %f2(int %a) {
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entry:
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%tmp = setgt int %a, 4 ; <bool> [#uses=1]
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%tmp1 = select bool %tmp, int 2, int 3
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ret int %tmp1
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}
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int %f3(int %a, int %b) {
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entry:
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%tmp = setlt int %a, %b ; <bool> [#uses=1]
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%tmp1 = select bool %tmp, int 2, int 3
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ret int %tmp1
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}
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int %f4(int %a, int %b) {
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entry:
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%tmp = setle int %a, %b ; <bool> [#uses=1]
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%tmp1 = select bool %tmp, int 2, int 3
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ret int %tmp1
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}
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int %f5(uint %a, uint %b) {
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entry:
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%tmp = setle uint %a, %b ; <bool> [#uses=1]
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%tmp1 = select bool %tmp, int 2, int 3
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ret int %tmp1
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}
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int %f6(uint %a, uint %b) {
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entry:
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%tmp = setgt uint %a, %b ; <bool> [#uses=1]
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%tmp1 = select bool %tmp, int 2, int 3
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ret int %tmp1
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}
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