diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td index f1d6f3d6bb7..5f273aaba79 100644 --- a/lib/Target/ARM64/ARM64InstrFormats.td +++ b/lib/Target/ARM64/ARM64InstrFormats.td @@ -1275,6 +1275,7 @@ class ADRI pattern> def movimm32_imm : Operand { let ParserMatchClass = Imm0_65535Operand; let EncoderMethod = "getMoveWideImmOpValue"; + let PrintMethod = "printHexImm"; } def movimm32_shift : Operand { let PrintMethod = "printShifter"; diff --git a/test/CodeGen/AArch64/cond-sel.ll b/test/CodeGen/AArch64/cond-sel.ll index 8d6ec8605a6..febb2204665 100644 --- a/test/CodeGen/AArch64/cond-sel.ll +++ b/test/CodeGen/AArch64/cond-sel.ll @@ -12,8 +12,8 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize { %tst1 = icmp ugt i32 %lhs32, %rhs32 %val1 = select i1 %tst1, i32 42, i32 52 store i32 %val1, i32* @var32 -; CHECK-DAG: movz [[W52:w[0-9]+]], #52 -; CHECK-DAG: movz [[W42:w[0-9]+]], #42 +; CHECK-DAG: movz [[W52:w[0-9]+]], #{{52|0x34}} +; CHECK-DAG: movz [[W42:w[0-9]+]], #{{42|0x2a}} ; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi %rhs64 = sext i32 %rhs32 to i64 @@ -36,8 +36,8 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r ; CHECK-NOFP-NOT: fcmp %val1 = select i1 %tst1, i32 42, i32 52 store i32 %val1, i32* @var32 -; CHECK: movz [[W52:w[0-9]+]], #52 -; CHECK: movz [[W42:w[0-9]+]], #42 +; CHECK: movz [[W52:w[0-9]+]], #{{52|0x34}} +; CHECK: movz [[W42:w[0-9]+]], #{{42|0x2a}} ; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi ; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt @@ -49,7 +49,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r store i64 %val2, i64* @var64 ; CHECK-AARCH64: movz x[[CONST15:[0-9]+]], #15 ; CHECK-ARM64: orr w[[CONST15:[0-9]+]], wzr, #0xf -; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #9 +; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}} ; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq ; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll index 538cf0bb607..26c705700a6 100644 --- a/test/CodeGen/AArch64/func-calls.ll +++ b/test/CodeGen/AArch64/func-calls.ll @@ -114,10 +114,10 @@ define void @check_stack_args() { ; CHECK-AARCH64: mov x0, sp ; CHECK-AARCH64: str d[[STACKEDREG]], [x0] -; CHECK-ARM64: movz [[SIXTY_FOUR:w[0-9]+]], #17024, lsl #16 +; CHECK-ARM64: movz [[SIXTY_FOUR:w[0-9]+]], #0x4280, lsl #16 ; CHECK-ARM64: str [[SIXTY_FOUR]], [sp] -; CHECK-ARM64-NONEON: movz [[SIXTY_FOUR:w[0-9]+]], #17024, lsl #16 +; CHECK-ARM64-NONEON: movz [[SIXTY_FOUR:w[0-9]+]], #0x4280, lsl #16 ; CHECK-ARM64-NONEON: str [[SIXTY_FOUR]], [sp] ; CHECK: bl stacked_fpu diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll index e783b988b56..876eb52df62 100644 --- a/test/CodeGen/AArch64/movw-consts.ll +++ b/test/CodeGen/AArch64/movw-consts.ll @@ -61,7 +61,7 @@ define i64 @test7() { ; couldn't. Useful even for i64 define i64 @test8() { ; CHECK-LABEL: test8: -; CHECK: movn w0, #60875 +; CHECK: movn w0, #{{60875|0xedcb}} ret i64 4294906420 } @@ -73,7 +73,7 @@ define i64 @test9() { define i64 @test10() { ; CHECK-LABEL: test10: -; CHECK: movn x0, #60875, lsl #16 +; CHECK: movn x0, #{{60875|0xedcb}}, lsl #16 ret i64 18446744069720047615 } diff --git a/test/CodeGen/ARM64/abi_align.ll b/test/CodeGen/ARM64/abi_align.ll index d8ec3958ba1..13a2a394f39 100644 --- a/test/CodeGen/ARM64/abi_align.ll +++ b/test/CodeGen/ARM64/abi_align.ll @@ -74,7 +74,7 @@ define i32 @caller38_stack() #1 { entry: ; CHECK: caller38_stack ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8] -; CHECK: movz w[[C:[0-9]+]], #9 +; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] %0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4 %1 = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 4 @@ -128,7 +128,7 @@ entry: ; CHECK: caller39_stack ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32] ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16] -; CHECK: movz w[[C:[0-9]+]], #9 +; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] %0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16 %1 = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 16 @@ -184,7 +184,7 @@ entry: ; CHECK: caller40_stack ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #24] ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8] -; CHECK: movz w[[C:[0-9]+]], #9 +; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] %0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4 %1 = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4 @@ -238,7 +238,7 @@ entry: ; CHECK: caller41_stack ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32] ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16] -; CHECK: movz w[[C:[0-9]+]], #9 +; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] %0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16 %1 = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 16 @@ -330,7 +330,7 @@ entry: ; CHECK: sub x[[A:[0-9]+]], x29, #32 ; Address of s1 is passed on stack at sp+8 ; CHECK: str x[[A]], [sp, #8] -; CHECK: movz w[[C:[0-9]+]], #9 +; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] ; FAST: caller42_stack @@ -442,7 +442,7 @@ entry: ; CHECK: sub x[[A:[0-9]+]], x29, #32 ; Address of s1 is passed on stack at sp+8 ; CHECK: str x[[A]], [sp, #8] -; CHECK: movz w[[C:[0-9]+]], #9 +; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] ; FAST: caller43_stack diff --git a/test/CodeGen/ARM64/atomic.ll b/test/CodeGen/ARM64/atomic.ll index b446f3e499b..aa9b284410b 100644 --- a/test/CodeGen/ARM64/atomic.ll +++ b/test/CodeGen/ARM64/atomic.ll @@ -57,7 +57,7 @@ define i64 @fetch_and_nand_64(i64* %p) { define i32 @fetch_and_or(i32* %p) { ; CHECK-LABEL: fetch_and_or: -; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #5 +; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]: ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0] ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]] diff --git a/test/CodeGen/ARM64/bitfield-extract.ll b/test/CodeGen/ARM64/bitfield-extract.ll index 143aebc5779..6de563c1eb6 100644 --- a/test/CodeGen/ARM64/bitfield-extract.ll +++ b/test/CodeGen/ARM64/bitfield-extract.ll @@ -348,8 +348,8 @@ entry: ; CHECK-LABEL: fct16: ; CHECK: ldr [[REG1:w[0-9]+]], ; Create the constant -; CHECK: movz [[REGCST:w[0-9]+]], #26, lsl #16 -; CHECK: movk [[REGCST]], #33120 +; CHECK: movz [[REGCST:w[0-9]+]], #0x1a, lsl #16 +; CHECK: movk [[REGCST]], #0x8160 ; Do the masking ; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]] ; CHECK-NEXT: bfm [[REG2]], w1, #16, #18 @@ -377,8 +377,8 @@ entry: ; CHECK-LABEL: fct17: ; CHECK: ldr [[REG1:x[0-9]+]], ; Create the constant -; CHECK: movz w[[REGCST:[0-9]+]], #26, lsl #16 -; CHECK: movk w[[REGCST]], #33120 +; CHECK: movz w[[REGCST:[0-9]+]], #0x1a, lsl #16 +; CHECK: movk w[[REGCST]], #0x8160 ; Do the masking ; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]] ; CHECK-NEXT: bfm [[REG2]], x1, #16, #18 diff --git a/test/CodeGen/ARM64/const-addr.ll b/test/CodeGen/ARM64/const-addr.ll index 977628a0921..c55a9226cc7 100644 --- a/test/CodeGen/ARM64/const-addr.ll +++ b/test/CodeGen/ARM64/const-addr.ll @@ -5,8 +5,8 @@ ; Test if the constant base address gets only materialized once. define i32 @test1() nounwind { ; CHECK-LABEL: test1 -; CHECK: movz w8, #1039, lsl #16 -; CHECK-NEXT: movk w8, #49152 +; CHECK: movz w8, #0x40f, lsl #16 +; CHECK-NEXT: movk w8, #0xc000 ; CHECK-NEXT: ldp w9, w10, [x8, #4] ; CHECK: ldr w8, [x8, #12] %at = inttoptr i64 68141056 to %T* diff --git a/test/CodeGen/ARM64/fast-isel-addr-offset.ll b/test/CodeGen/ARM64/fast-isel-addr-offset.ll index a4326dc2b85..ebd847e0f72 100644 --- a/test/CodeGen/ARM64/fast-isel-addr-offset.ll +++ b/test/CodeGen/ARM64/fast-isel-addr-offset.ll @@ -9,7 +9,7 @@ entry: ; CHECK: @foo ; CHECK: adrp x[[REG:[0-9]+]], _sortlist@GOTPAGE ; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist@GOTPAGEOFF] -; CHECK: movz x[[REG2:[0-9]+]], #20000 +; CHECK: movz x[[REG2:[0-9]+]], #0x4e20 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]] ; CHECK: ldr w0, [x[[REG3]]] ; CHECK: ret @@ -22,7 +22,7 @@ entry: ; CHECK: @foo2 ; CHECK: adrp x[[REG:[0-9]+]], _sortlist2@GOTPAGE ; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist2@GOTPAGEOFF] -; CHECK: movz x[[REG2:[0-9]+]], #40000 +; CHECK: movz x[[REG2:[0-9]+]], #0x9c40 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]] ; CHECK: ldr x0, [x[[REG3]]] ; CHECK: ret @@ -37,9 +37,9 @@ entry: define signext i8 @foo3() nounwind ssp { entry: ; CHECK: @foo3 -; CHECK: movz x[[REG:[0-9]+]], #2874, lsl #32 -; CHECK: movk x[[REG]], #29646, lsl #16 -; CHECK: movk x[[REG]], #12274 +; CHECK: movz x[[REG:[0-9]+]], #0xb3a, lsl #32 +; CHECK: movk x[[REG]], #0x73ce, lsl #16 +; CHECK: movk x[[REG]], #0x2ff2 %0 = load i8** @pd2, align 8 %arrayidx = getelementptr inbounds i8* %0, i64 12345678901234 %1 = load i8* %arrayidx, align 1 diff --git a/test/CodeGen/ARM64/fast-isel-gv.ll b/test/CodeGen/ARM64/fast-isel-gv.ll index cb3df1412c8..dc4d8953c27 100644 --- a/test/CodeGen/ARM64/fast-isel-gv.ll +++ b/test/CodeGen/ARM64/fast-isel-gv.ll @@ -18,10 +18,10 @@ entry: ; CHECK: @Rand ; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE ; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF] -; CHECK: movz x[[REG3:[0-9]+]], #1309 +; CHECK: movz x[[REG3:[0-9]+]], #0x51d ; CHECK: ldr x[[REG4:[0-9]+]], [x[[REG2]]] ; CHECK: mul x[[REG5:[0-9]+]], x[[REG4]], x[[REG3]] -; CHECK: movz x[[REG6:[0-9]+]], #13849 +; CHECK: movz x[[REG6:[0-9]+]], #0x3619 ; CHECK: add x[[REG7:[0-9]+]], x[[REG5]], x[[REG6]] ; CHECK: orr x[[REG8:[0-9]+]], xzr, #0xffff ; CHECK: and x[[REG9:[0-9]+]], x[[REG7]], x[[REG8]] diff --git a/test/CodeGen/ARM64/fast-isel-intrinsic.ll b/test/CodeGen/ARM64/fast-isel-intrinsic.ll index 6443d82e2cc..a3d5f6c3c5a 100644 --- a/test/CodeGen/ARM64/fast-isel-intrinsic.ll +++ b/test/CodeGen/ARM64/fast-isel-intrinsic.ll @@ -4,11 +4,11 @@ @temp = common global [80 x i8] zeroinitializer, align 16 define void @t1() { -; ARM64: t1 +; ARM64-LABEL: t1 ; ARM64: adrp x8, _message@PAGE ; ARM64: add x0, x8, _message@PAGEOFF ; ARM64: movz w9, #0 -; ARM64: movz x2, #80 +; ARM64: movz x2, #0x50 ; ARM64: uxtb w1, w9 ; ARM64: bl _memset call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false) @@ -18,12 +18,12 @@ define void @t1() { declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) define void @t2() { -; ARM64: t2 +; ARM64-LABEL: t2 ; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: ldr x0, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x8, _message@PAGE ; ARM64: add x1, x8, _message@PAGEOFF -; ARM64: movz x2, #80 +; ARM64: movz x2, #0x50 ; ARM64: bl _memcpy call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false) ret void @@ -32,12 +32,12 @@ define void @t2() { declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) define void @t3() { -; ARM64: t3 +; ARM64-LABEL: t3 ; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: ldr x0, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x8, _message@PAGE ; ARM64: add x1, x8, _message@PAGEOFF -; ARM64: movz x2, #20 +; ARM64: movz x2, #0x14 ; ARM64: bl _memmove call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false) ret void @@ -46,7 +46,7 @@ define void @t3() { declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) define void @t4() { -; ARM64: t4 +; ARM64-LABEL: t4 ; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x9, _message@PAGE @@ -63,7 +63,7 @@ define void @t4() { } define void @t5() { -; ARM64: t5 +; ARM64-LABEL: t5 ; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x9, _message@PAGE @@ -80,7 +80,7 @@ define void @t5() { } define void @t6() { -; ARM64: t6 +; ARM64-LABEL: t6 ; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x9, _message@PAGE @@ -97,7 +97,7 @@ define void @t6() { } define void @t7() { -; ARM64: t7 +; ARM64-LABEL: t7 ; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x9, _message@PAGE @@ -116,7 +116,7 @@ define void @t7() { } define void @t8() { -; ARM64: t8 +; ARM64-LABEL: t8 ; ARM64: adrp x8, _temp@GOTPAGE ; ARM64: ldr x8, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x9, _message@PAGE diff --git a/test/CodeGen/ARM64/fp128.ll b/test/CodeGen/ARM64/fp128.ll index a1a956d2317..a481c79cca1 100644 --- a/test/CodeGen/ARM64/fp128.ll +++ b/test/CodeGen/ARM64/fp128.ll @@ -186,13 +186,13 @@ define i32 @test_br_cc() { iftrue: ret i32 42 ; CHECK-NEXT: BB# -; CHECK-NEXT: movz w0, #42 +; CHECK-NEXT: movz w0, #0x2a ; CHECK-NEXT: b [[REALRET:.LBB[0-9]+_[0-9]+]] iffalse: ret i32 29 ; CHECK: [[RET29]]: -; CHECK-NEXT: movz w0, #29 +; CHECK-NEXT: movz w0, #0x1d ; CHECK-NEXT: [[REALRET]]: ; CHECK: ret } diff --git a/test/CodeGen/ARM64/memcpy-inline.ll b/test/CodeGen/ARM64/memcpy-inline.ll index 26f51668941..f921a592451 100644 --- a/test/CodeGen/ARM64/memcpy-inline.ll +++ b/test/CodeGen/ARM64/memcpy-inline.ll @@ -75,7 +75,7 @@ define void @t5(i8* nocapture %C) nounwind { entry: ; CHECK-LABEL: t5: ; CHECK: strb wzr, [x0, #6] -; CHECK: movz [[REG7:w[0-9]+]], #21587 +; CHECK: movz [[REG7:w[0-9]+]], #0x5453 ; CHECK: strh [[REG7]], [x0, #4] ; CHECK: movz [[REG8:w[0-9]+]], ; CHECK: movk [[REG8]], diff --git a/test/CodeGen/ARM64/movi.ll b/test/CodeGen/ARM64/movi.ll index 8fcecccd5b2..2cd368d909d 100644 --- a/test/CodeGen/ARM64/movi.ll +++ b/test/CodeGen/ARM64/movi.ll @@ -6,35 +6,35 @@ ; 64-bit immed with 32-bit pattern size, rotated by 0. define i64 @test64_32_rot0() nounwind { -; CHECK: test64_32_rot0 +; CHECK-LABEL: test64_32_rot0: ; CHECK: orr x0, xzr, #0x700000007 ret i64 30064771079 } ; 64-bit immed with 32-bit pattern size, rotated by 2. define i64 @test64_32_rot2() nounwind { -; CHECK: test64_32_rot2 +; CHECK-LABEL: test64_32_rot2: ; CHECK: orr x0, xzr, #0xc0000003c0000003 ret i64 13835058071388291075 } ; 64-bit immed with 4-bit pattern size, rotated by 3. define i64 @test64_4_rot3() nounwind { -; CHECK: test64_4_rot3 +; CHECK-LABEL: test64_4_rot3: ; CHECK: orr x0, xzr, #0xeeeeeeeeeeeeeeee ret i64 17216961135462248174 } ; 32-bit immed with 32-bit pattern size, rotated by 16. define i32 @test32_32_rot16() nounwind { -; CHECK: test32_32_rot16 +; CHECK-LABEL: test32_32_rot16: ; CHECK: orr w0, wzr, #0xff0000 ret i32 16711680 } ; 32-bit immed with 2-bit pattern size, rotated by 1. define i32 @test32_2_rot1() nounwind { -; CHECK: test32_2_rot1 +; CHECK-LABEL: test32_2_rot1: ; CHECK: orr w0, wzr, #0xaaaaaaaa ret i32 2863311530 } @@ -44,31 +44,31 @@ define i32 @test32_2_rot1() nounwind { ;==--------------------------------------------------------------------------== define i32 @movz() nounwind { -; CHECK: movz -; CHECK: movz w0, #5 +; CHECK-LABEL: movz: +; CHECK: movz w0, #0x5 ret i32 5 } define i64 @movz_3movk() nounwind { -; CHECK: movz_3movk -; CHECK: movz x0, #5, lsl #48 -; CHECK-NEXT: movk x0, #4660, lsl #32 -; CHECK-NEXT: movk x0, #43981, lsl #16 -; CHECK-NEXT: movk x0, #22136 +; CHECK-LABEL: movz_3movk: +; CHECK: movz x0, #0x5, lsl #48 +; CHECK-NEXT: movk x0, #0x1234, lsl #32 +; CHECK-NEXT: movk x0, #0xabcd, lsl #16 +; CHECK-NEXT: movk x0, #0x5678 ret i64 1427392313513592 } define i64 @movz_movk_skip1() nounwind { -; CHECK: movz_movk_skip1 -; CHECK: movz x0, #5, lsl #32 -; CHECK-NEXT: movk x0, #17185, lsl #16 +; CHECK-LABEL: movz_movk_skip1: +; CHECK: movz x0, #0x5, lsl #32 +; CHECK-NEXT: movk x0, #0x4321, lsl #16 ret i64 22601072640 } define i64 @movz_skip1_movk() nounwind { -; CHECK: movz_skip1_movk -; CHECK: movz x0, #34388, lsl #32 -; CHECK-NEXT: movk x0, #4660 +; CHECK-LABEL: movz_skip1_movk: +; CHECK: movz x0, #0x8654, lsl #32 +; CHECK-NEXT: movk x0, #0x1234 ret i64 147695335379508 } @@ -77,15 +77,15 @@ define i64 @movz_skip1_movk() nounwind { ;==--------------------------------------------------------------------------== define i64 @movn() nounwind { -; CHECK: movn -; CHECK: movn x0, #41 +; CHECK-LABEL: movn: +; CHECK: movn x0, #0x29 ret i64 -42 } define i64 @movn_skip1_movk() nounwind { -; CHECK: movn_skip1_movk -; CHECK: movn x0, #41, lsl #32 -; CHECK-NEXT: movk x0, #4660 +; CHECK-LABEL: movn_skip1_movk: +; CHECK: movn x0, #0x29, lsl #32 +; CHECK-NEXT: movk x0, #0x1234 ret i64 -176093720012 } @@ -95,108 +95,108 @@ define i64 @movn_skip1_movk() nounwind { ; rdar://14987673 define i64 @orr_movk1() nounwind { -; CHECK: orr_movk1 +; CHECK-LABEL: orr_movk1: ; CHECK: orr x0, xzr, #0xffff0000ffff0 -; CHECK: movk x0, #57005, lsl #16 +; CHECK: movk x0, #0xdead, lsl #16 ret i64 72056498262245120 } define i64 @orr_movk2() nounwind { -; CHECK: orr_movk2 +; CHECK-LABEL: orr_movk2: ; CHECK: orr x0, xzr, #0xffff0000ffff0 -; CHECK: movk x0, #57005, lsl #48 +; CHECK: movk x0, #0xdead, lsl #48 ret i64 -2400982650836746496 } define i64 @orr_movk3() nounwind { -; CHECK: orr_movk3 +; CHECK-LABEL: orr_movk3: ; CHECK: orr x0, xzr, #0xffff0000ffff0 -; CHECK: movk x0, #57005, lsl #32 +; CHECK: movk x0, #0xdead, lsl #32 ret i64 72020953688702720 } define i64 @orr_movk4() nounwind { -; CHECK: orr_movk4 +; CHECK-LABEL: orr_movk4: ; CHECK: orr x0, xzr, #0xffff0000ffff0 -; CHECK: movk x0, #57005 +; CHECK: movk x0, #0xdead ret i64 72056494543068845 } ; rdar://14987618 define i64 @orr_movk5() nounwind { -; CHECK: orr_movk5 +; CHECK-LABEL: orr_movk5: ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00 -; CHECK: movk x0, #57005, lsl #16 +; CHECK: movk x0, #0xdead, lsl #16 ret i64 -71777214836900096 } define i64 @orr_movk6() nounwind { -; CHECK: orr_movk6 +; CHECK-LABEL: orr_movk6: ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00 -; CHECK: movk x0, #57005, lsl #16 -; CHECK: movk x0, #57005, lsl #48 +; CHECK: movk x0, #0xdead, lsl #16 +; CHECK: movk x0, #0xdead, lsl #48 ret i64 -2400982647117578496 } define i64 @orr_movk7() nounwind { -; CHECK: orr_movk7 +; CHECK-LABEL: orr_movk7: ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00 -; CHECK: movk x0, #57005, lsl #48 +; CHECK: movk x0, #0xdead, lsl #48 ret i64 -2400982646575268096 } define i64 @orr_movk8() nounwind { -; CHECK: orr_movk8 +; CHECK-LABEL: orr_movk8: ; CHECK: orr x0, xzr, #0xff00ff00ff00ff00 -; CHECK: movk x0, #57005 -; CHECK: movk x0, #57005, lsl #48 +; CHECK: movk x0, #0xdead +; CHECK: movk x0, #0xdead, lsl #48 ret i64 -2400982646575276371 } ; rdar://14987715 define i64 @orr_movk9() nounwind { -; CHECK: orr_movk9 +; CHECK-LABEL: orr_movk9: ; CHECK: orr x0, xzr, #0xffffff000000000 -; CHECK: movk x0, #65280 -; CHECK: movk x0, #57005, lsl #16 +; CHECK: movk x0, #0xff00 +; CHECK: movk x0, #0xdead, lsl #16 ret i64 1152921439623315200 } define i64 @orr_movk10() nounwind { -; CHECK: orr_movk10 +; CHECK-LABEL: orr_movk10: ; CHECK: orr x0, xzr, #0xfffffffffffff00 -; CHECK: movk x0, #57005, lsl #16 +; CHECK: movk x0, #0xdead, lsl #16 ret i64 1152921504047824640 } define i64 @orr_movk11() nounwind { -; CHECK: orr_movk11 +; CHECK-LABEL: orr_movk11: ; CHECK: orr x0, xzr, #0xfff00000000000ff -; CHECK: movk x0, #57005, lsl #16 -; CHECK: movk x0, #65535, lsl #32 +; CHECK: movk x0, #0xdead, lsl #16 +; CHECK: movk x0, #0xffff, lsl #32 ret i64 -4222125209747201 } define i64 @orr_movk12() nounwind { -; CHECK: orr_movk12 +; CHECK-LABEL: orr_movk12: ; CHECK: orr x0, xzr, #0xfff00000000000ff -; CHECK: movk x0, #57005, lsl #32 +; CHECK: movk x0, #0xdead, lsl #32 ret i64 -4258765016661761 } define i64 @orr_movk13() nounwind { -; CHECK: orr_movk13 +; CHECK-LABEL: orr_movk13: ; CHECK: orr x0, xzr, #0xfffff000000 -; CHECK: movk x0, #57005 -; CHECK: movk x0, #57005, lsl #48 +; CHECK: movk x0, #0xdead +; CHECK: movk x0, #0xdead, lsl #48 ret i64 -2401245434149282131 } ; rdar://13944082 define i64 @g() nounwind { -; CHECK: g -; CHECK: movz x0, #65535, lsl #48 -; CHECK: movk x0, #2 +; CHECK-LABEL: g: +; CHECK: movz x0, #0xffff, lsl #48 +; CHECK: movk x0, #0x2 entry: ret i64 -281474976710654 } diff --git a/test/CodeGen/ARM64/patchpoint.ll b/test/CodeGen/ARM64/patchpoint.ll index dd555b0f3e5..9ef1d778a31 100644 --- a/test/CodeGen/ARM64/patchpoint.ll +++ b/test/CodeGen/ARM64/patchpoint.ll @@ -5,13 +5,13 @@ define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: ; CHECK-LABEL: trivial_patchpoint_codegen: -; CHECK: movz x16, #57005, lsl #32 -; CHECK-NEXT: movk x16, #48879, lsl #16 -; CHECK-NEXT: movk x16, #51966 +; CHECK: movz x16, #0xdead, lsl #32 +; CHECK-NEXT: movk x16, #0xbeef, lsl #16 +; CHECK-NEXT: movk x16, #0xcafe ; CHECK-NEXT: blr x16 -; CHECK: movz x16, #57005, lsl #32 -; CHECK-NEXT: movk x16, #48879, lsl #16 -; CHECK-NEXT: movk x16, #51967 +; CHECK: movz x16, #0xdead, lsl #32 +; CHECK-NEXT: movk x16, #0xbeef, lsl #16 +; CHECK-NEXT: movk x16, #0xcaff ; CHECK-NEXT: blr x16 ; CHECK: ret %resolveCall2 = inttoptr i64 244837814094590 to i8* @@ -51,9 +51,9 @@ entry: ; CHECK: str x{{.+}}, [sp] ; CHECK-NEXT: mov x0, x{{.+}} ; CHECK: Ltmp -; CHECK-NEXT: movz x16, #65535, lsl #32 -; CHECK-NEXT: movk x16, #57005, lsl #16 -; CHECK-NEXT: movk x16, #48879 +; CHECK-NEXT: movz x16, #0xffff, lsl #32 +; CHECK-NEXT: movk x16, #0xdead, lsl #16 +; CHECK-NEXT: movk x16, #0xbeef ; CHECK-NEXT: blr x16 %resolveCall2 = inttoptr i64 281474417671919 to i8* %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2) @@ -74,9 +74,9 @@ entry: ; CHECK-NEXT: orr w{{.+}}, wzr, #0x2 ; CHECK-NEXT: str x{{.+}}, [sp] ; CHECK: Ltmp -; CHECK-NEXT: movz x16, #65535, lsl #32 -; CHECK-NEXT: movk x16, #57005, lsl #16 -; CHECK-NEXT: movk x16, #48879 +; CHECK-NEXT: movz x16, #0xffff, lsl #32 +; CHECK-NEXT: movk x16, #0xdead, lsl #16 +; CHECK-NEXT: movk x16, #0xbeef ; CHECK-NEXT: blr x16 %call = inttoptr i64 281474417671919 to i8* %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6) @@ -88,7 +88,7 @@ define i64 @jscall_patchpoint_codegen3(i64 %callee) { entry: ; CHECK-LABEL: jscall_patchpoint_codegen3: ; CHECK: Ltmp -; CHECK: movz w{{.+}}, #10 +; CHECK: movz w{{.+}}, #0xa ; CHECK-NEXT: str x{{.+}}, [sp, #48] ; CHECK-NEXT: orr w{{.+}}, wzr, #0x8 ; CHECK-NEXT: str w{{.+}}, [sp, #36] @@ -99,9 +99,9 @@ entry: ; CHECK-NEXT: orr w{{.+}}, wzr, #0x2 ; CHECK-NEXT: str x{{.+}}, [sp] ; CHECK: Ltmp -; CHECK-NEXT: movz x16, #65535, lsl #32 -; CHECK-NEXT: movk x16, #57005, lsl #16 -; CHECK-NEXT: movk x16, #48879 +; CHECK-NEXT: movz x16, #0xffff, lsl #32 +; CHECK-NEXT: movk x16, #0xdead, lsl #16 +; CHECK-NEXT: movk x16, #0xbeef ; CHECK-NEXT: blr x16 %call = inttoptr i64 281474417671919 to i8* %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10) diff --git a/test/CodeGen/ARM64/register-pairing.ll b/test/CodeGen/ARM64/register-pairing.ll index 4de80d2d2e7..99defb1aad7 100644 --- a/test/CodeGen/ARM64/register-pairing.ll +++ b/test/CodeGen/ARM64/register-pairing.ll @@ -13,7 +13,7 @@ define void @odd() nounwind { ; CHECK: stp x24, x23, [sp, #96] ; CHECK: stp x22, x21, [sp, #112] ; CHECK: stp x20, x19, [sp, #128] -; CHECK: movz x0, #42 +; CHECK: movz x0, #0x2a ; CHECK: ldp x20, x19, [sp, #128] ; CHECK: ldp x22, x21, [sp, #112] ; CHECK: ldp x24, x23, [sp, #96] @@ -38,7 +38,7 @@ define void @even() nounwind { ; CHECK: stp x24, x23, [sp, #96] ; CHECK: stp x22, x21, [sp, #112] ; CHECK: stp x20, x19, [sp, #128] -; CHECK: movz x0, #42 +; CHECK: movz x0, #0x2a ; CHECK: ldp x20, x19, [sp, #128] ; CHECK: ldp x22, x21, [sp, #112] ; CHECK: ldp x24, x23, [sp, #96] diff --git a/test/CodeGen/ARM64/variadic-aapcs.ll b/test/CodeGen/ARM64/variadic-aapcs.ll index ac66902fa66..36a7bfd9252 100644 --- a/test/CodeGen/ARM64/variadic-aapcs.ll +++ b/test/CodeGen/ARM64/variadic-aapcs.ll @@ -32,7 +32,7 @@ define void @test_simple(i32 %n, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: movn [[GR_OFFS:w[0-9]+]], #55 +; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x37 ; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] ; CHECK: orr [[VR_OFFS:w[0-9]+]], wzr, #0xffffff80 @@ -70,10 +70,10 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: movn [[GR_OFFS:w[0-9]+]], #39 +; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x27 ; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] -; CHECK: movn [[VR_OFFS:w[0-9]+]], #111 +; CHECK: movn [[VR_OFFS:w[0-9]+]], #0x6f ; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] %addr = bitcast %va_list* @var to i8* diff --git a/test/MC/ARM64/aliases.s b/test/MC/ARM64/aliases.s index 5c2f15cccc6..2bae11459a0 100644 --- a/test/MC/ARM64/aliases.s +++ b/test/MC/ARM64/aliases.s @@ -134,8 +134,8 @@ foo: mov x0, #281470681743360 mov x0, #18446744073709486080 -; CHECK: movz x0, #65535, lsl #32 -; CHECK: movn x0, #65535 +; CHECK: movz x0, #0xffff, lsl #32 +; CHECK: movn x0, #0xffff mov w0, #0xffffffff mov w0, #0xffffff00 @@ -143,9 +143,9 @@ foo: mov wzr, #0xffffff00 ; CHECK: movn w0, #0 -; CHECK: movn w0, #255 +; CHECK: movn w0, #0xff ; CHECK: movn wzr, #0 -; CHECK: movn wzr, #255 +; CHECK: movn wzr, #0xff ;----------------------------------------------------------------------------- ; MVN aliases diff --git a/test/MC/ARM64/arithmetic-encoding.s b/test/MC/ARM64/arithmetic-encoding.s index 6dd8ba1521a..4b5e151f549 100644 --- a/test/MC/ARM64/arithmetic-encoding.s +++ b/test/MC/ARM64/arithmetic-encoding.s @@ -510,30 +510,30 @@ foo: movz w0, #1, lsl #16 movz x0, #1, lsl #16 -; CHECK: movz w0, #1 ; encoding: [0x20,0x00,0x80,0x52] -; CHECK: movz x0, #1 ; encoding: [0x20,0x00,0x80,0xd2] -; CHECK: movz w0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x52] -; CHECK: movz x0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xd2] +; CHECK: movz w0, #0x1 ; encoding: [0x20,0x00,0x80,0x52] +; CHECK: movz x0, #0x1 ; encoding: [0x20,0x00,0x80,0xd2] +; CHECK: movz w0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x52] +; CHECK: movz x0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xd2] movn w0, #2 movn x0, #2 movn w0, #2, lsl #16 movn x0, #2, lsl #16 -; CHECK: movn w0, #2 ; encoding: [0x40,0x00,0x80,0x12] -; CHECK: movn x0, #2 ; encoding: [0x40,0x00,0x80,0x92] -; CHECK: movn w0, #2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x12] -; CHECK: movn x0, #2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x92] +; CHECK: movn w0, #0x2 ; encoding: [0x40,0x00,0x80,0x12] +; CHECK: movn x0, #0x2 ; encoding: [0x40,0x00,0x80,0x92] +; CHECK: movn w0, #0x2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x12] +; CHECK: movn x0, #0x2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x92] movk w0, #1 movk x0, #1 movk w0, #1, lsl #16 movk x0, #1, lsl #16 -; CHECK: movk w0, #1 ; encoding: [0x20,0x00,0x80,0x72] -; CHECK: movk x0, #1 ; encoding: [0x20,0x00,0x80,0xf2] -; CHECK: movk w0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x72] -; CHECK: movk x0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xf2] +; CHECK: movk w0, #0x1 ; encoding: [0x20,0x00,0x80,0x72] +; CHECK: movk x0, #0x1 ; encoding: [0x20,0x00,0x80,0xf2] +; CHECK: movk w0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x72] +; CHECK: movk x0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xf2] ;==---------------------------------------------------------------------------== ; Conditionally set flags instructions diff --git a/test/MC/Disassembler/ARM64/arithmetic.txt b/test/MC/Disassembler/ARM64/arithmetic.txt index 5e98fca9592..7e18fc631ca 100644 --- a/test/MC/Disassembler/ARM64/arithmetic.txt +++ b/test/MC/Disassembler/ARM64/arithmetic.txt @@ -452,30 +452,30 @@ 0x20 0x00 0xa0 0x52 0x20 0x00 0xa0 0xd2 -# CHECK: movz w0, #1 -# CHECK: movz x0, #1 -# CHECK: movz w0, #1, lsl #16 -# CHECK: movz x0, #1, lsl #16 +# CHECK: movz w0, #0x1 +# CHECK: movz x0, #0x1 +# CHECK: movz w0, #0x1, lsl #16 +# CHECK: movz x0, #0x1, lsl #16 0x40 0x00 0x80 0x12 0x40 0x00 0x80 0x92 0x40 0x00 0xa0 0x12 0x40 0x00 0xa0 0x92 -# CHECK: movn w0, #2 -# CHECK: movn x0, #2 -# CHECK: movn w0, #2, lsl #16 -# CHECK: movn x0, #2, lsl #16 +# CHECK: movn w0, #0x2 +# CHECK: movn x0, #0x2 +# CHECK: movn w0, #0x2, lsl #16 +# CHECK: movn x0, #0x2, lsl #16 0x20 0x00 0x80 0x72 0x20 0x00 0x80 0xf2 0x20 0x00 0xa0 0x72 0x20 0x00 0xa0 0xf2 -# CHECK: movk w0, #1 -# CHECK: movk x0, #1 -# CHECK: movk w0, #1, lsl #16 -# CHECK: movk x0, #1, lsl #16 +# CHECK: movk w0, #0x1 +# CHECK: movk x0, #0x1 +# CHECK: movk w0, #0x1, lsl #16 +# CHECK: movk x0, #0x1, lsl #16 #==---------------------------------------------------------------------------== # Conditionally set flags instructions