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Eliminate the use of dominance frontiers in PromoteMemToReg. In addition to

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eliminating a potentially quadratic data structure, this also gives a 17%
speedup when running -scalarrepl on test-suite + SPEC2000 + SPEC2006. My initial
experiment gave a greater speedup around 25%, but I moved the dominator tree
level computation from dominator tree construction to PromoteMemToReg.

Since this approach to computing IDFs has a much lower overhead than the old
code using precomputed DFs, it is worth looking at using this new code for the
second scalarrepl pass as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123609 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich
2011-01-17 01:08:59 +00:00
parent e7a820c208
commit ebed6de7b1
4 changed files with 124 additions and 64 deletions
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3
include/llvm/Transforms/Utils/PromoteMemToReg.h
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@ -38,8 +38,7 @@ bool isAllocaPromotable(const AllocaInst *AI);
/// made to the IR.
///
void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
DominatorTree &DT, DominanceFrontier &DF,
AliasSetTracker *AST = 0);
DominatorTree &DT, AliasSetTracker *AST = 0);
} // End llvm namespace