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R600/SI: Remove i1 pseudo VALU ops

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Select i1 logical ops directly to 64-bit SALU instructions.
Vector i1 values are always really in SGPRs, with each
bit for each item in the wave. This saves about 4 instructions
when and/or/xoring any condition, and also helps write conditions
that need to be passed in vcc.

This should work correctly now that the SGPR live range
fixing pass works. More work is needed to eliminate the VReg_1
pseudo regclass and possibly the entire SILowerI1Copies pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223206 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-12-03 05:22:35 +00:00
parent bd5f9f45d1
commit ec0a7cd15a
10 changed files with 339 additions and 124 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
test/CodeGen/R600/setcc.ll
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@@ -96,11 +96,12 @@ entry:
; R600-DAG: SETNE_DX10
; R600-DAG: AND_INT
; R600-DAG: SETNE_INT
; SI: v_cmp_o_f32
; SI: v_cmp_neq_f32
; SI: v_cndmask_b32_e64
; SI: v_cndmask_b32_e64
; SI: v_and_b32_e32
; SI-DAG: v_cmp_o_f32_e32 vcc
; SI-DAG: v_cmp_neq_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
; SI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP1]], vcc
; SI: v_cndmask_b32_e64 [[VRESULT:v[0-9]+]], 0, -1, [[AND]]
; SI: buffer_store_dword [[VRESULT]]
define void @f32_one(i32 addrspace(1)* %out, float %a, float %b) {
entry:
%0 = fcmp one float %a, %b
@@ -130,11 +131,12 @@ entry:
; R600-DAG: SETE_DX10
; R600-DAG: OR_INT
; R600-DAG: SETNE_INT
; SI: v_cmp_u_f32
; SI: v_cmp_eq_f32
; SI: v_cndmask_b32_e64
; SI: v_cndmask_b32_e64
; SI: v_or_b32_e32
; SI-DAG: v_cmp_u_f32_e32 vcc
; SI-DAG: v_cmp_eq_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
; SI: s_or_b64 [[OR:s\[[0-9]+:[0-9]+\]]], [[CMP1]], vcc
; SI: v_cndmask_b32_e64 [[VRESULT:v[0-9]+]], 0, -1, [[OR]]
; SI: buffer_store_dword [[VRESULT]]
define void @f32_ueq(i32 addrspace(1)* %out, float %a, float %b) {
entry:
%0 = fcmp ueq float %a, %b
@@ -148,9 +150,8 @@ entry:
; R600: SETE_DX10
; SI: v_cmp_u_f32
; SI: v_cmp_gt_f32
; SI: v_cndmask_b32_e64
; SI: v_cndmask_b32_e64
; SI: v_or_b32_e32
; SI: s_or_b64
; SI: v_cndmask_b32
define void @f32_ugt(i32 addrspace(1)* %out, float %a, float %b) {
entry:
%0 = fcmp ugt float %a, %b
@@ -164,9 +165,8 @@ entry:
; R600: SETE_DX10
; SI: v_cmp_u_f32
; SI: v_cmp_ge_f32
; SI: v_cndmask_b32_e64
; SI: v_cndmask_b32_e64
; SI: v_or_b32_e32
; SI: s_or_b64
; SI: v_cndmask_b32
define void @f32_uge(i32 addrspace(1)* %out, float %a, float %b) {
entry:
%0 = fcmp uge float %a, %b
@@ -180,9 +180,8 @@ entry:
; R600: SETE_DX10
; SI: v_cmp_u_f32
; SI: v_cmp_lt_f32
; SI: v_cndmask_b32_e64
; SI: v_cndmask_b32_e64
; SI: v_or_b32_e32
; SI: s_or_b64
; SI: v_cndmask_b32
define void @f32_ult(i32 addrspace(1)* %out, float %a, float %b) {
entry:
%0 = fcmp ult float %a, %b
@@ -196,9 +195,8 @@ entry:
; R600: SETE_DX10
; SI: v_cmp_u_f32
; SI: v_cmp_le_f32
; SI: v_cndmask_b32_e64
; SI: v_cndmask_b32_e64
; SI: v_or_b32_e32
; SI: s_or_b64
; SI: v_cndmask_b32
define void @f32_ule(i32 addrspace(1)* %out, float %a, float %b) {
entry:
%0 = fcmp ule float %a, %b