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Clean up a bunch of whitespace issues and fix a comment typo.

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No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68808 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2009-04-10 18:48:47 +00:00
parent 6818985032
commit ec15bbfd2f
1 changed files with 74 additions and 72 deletions
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74
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@@ -685,7 +685,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
// Perform the original store, only redirected to the stack slot. // Perform the original store, only redirected to the stack slot.
SDValue Store = DAG.getTruncStore(Chain, dl, SDValue Store = DAG.getTruncStore(Chain, dl,
Val, StackPtr, NULL, 0,StoredVT); Val, StackPtr, NULL, 0, StoredVT);
SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
SmallVector<SDValue, 8> Stores; SmallVector<SDValue, 8> Stores;
unsigned Offset = 0; unsigned Offset = 0;
@@ -864,7 +864,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
MinAlign(Alignment, IncrementSize)); MinAlign(Alignment, IncrementSize));
} else { } else {
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
SVOffset, NewLoadedVT,LD->isVolatile(), Alignment); SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, TLI.getPointerTy())); DAG.getConstant(IncrementSize, TLI.getPointerTy()));
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
@@ -1709,7 +1709,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
// Allow targets to custom lower the SHUFFLEs they support. // Allow targets to custom lower the SHUFFLEs they support.
switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType())){
default: assert(0 && "Unknown operation action!"); default: assert(0 && "Unknown operation action!");
case TargetLowering::Legal: case TargetLowering::Legal:
assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
@@ -1728,7 +1728,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
MVT PtrVT = TLI.getPointerTy(); MVT PtrVT = TLI.getPointerTy();
SDValue Mask = Node->getOperand(2); SDValue Mask = Node->getOperand(2);
unsigned NumElems = Mask.getNumOperands(); unsigned NumElems = Mask.getNumOperands();
SmallVector<SDValue,8> Ops; SmallVector<SDValue, 8> Ops;
for (unsigned i = 0; i != NumElems; ++i) { for (unsigned i = 0; i != NumElems; ++i) {
SDValue Arg = Mask.getOperand(i); SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) { if (Arg.getOpcode() == ISD::UNDEF) {
@@ -2475,7 +2475,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
if (Hi.getNode()) if (Hi.getNode())
Result = DAG.getNode(ISD::RET, dl, MVT::Other, Result = DAG.getNode(ISD::RET, dl, MVT::Other,
Tmp1, Lo, Tmp3, Hi,Tmp3); Tmp1, Lo, Tmp3, Hi, Tmp3);
else else
Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3); Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
Result = LegalizeOp(Result); Result = LegalizeOp(Result);
@@ -2510,7 +2510,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
SDValue Lo, Hi; SDValue Lo, Hi;
SplitVectorOp(Tmp2, Lo, Hi); SplitVectorOp(Tmp2, Lo, Hi);
Result = DAG.getNode(ISD::RET, dl, MVT::Other, Result = DAG.getNode(ISD::RET, dl, MVT::Other,
Tmp1, Lo, Tmp3, Hi,Tmp3); Tmp1, Lo, Tmp3, Hi, Tmp3);
Result = LegalizeOp(Result); Result = LegalizeOp(Result);
} }
} }
@@ -3009,7 +3009,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2); Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3); Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
// Perform the larger operation, then round down. // Perform the larger operation, then round down.
Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3); Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
if (TruncOp != ISD::FP_ROUND) if (TruncOp != ISD::FP_ROUND)
Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result); Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
else else
@@ -3147,9 +3147,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
TmpEltVT, Tmp2, TmpEltVT, Tmp2,
DAG.getIntPtrConstant(i)), DAG.getIntPtrConstant(i)),
CC); CC);
Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant( Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
APInt::getAllOnesValue(EltVT.getSizeInBits()), DAG.getConstant(APInt::getAllOnesValue
EltVT), DAG.getConstant(0, EltVT)); (EltVT.getSizeInBits()), EltVT),
DAG.getConstant(0, EltVT));
} }
Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
break; break;
@@ -4361,7 +4362,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// If this operation is not supported, lower it to 'abort()' call // If this operation is not supported, lower it to 'abort()' call
Tmp1 = LegalizeOp(Node->getOperand(0)); Tmp1 = LegalizeOp(Node->getOperand(0));
TargetLowering::ArgListTy Args; TargetLowering::ArgListTy Args;
std::pair<SDValue,SDValue> CallResult = std::pair<SDValue, SDValue> CallResult =
TLI.LowerCallTo(Tmp1, Type::VoidTy, TLI.LowerCallTo(Tmp1, Type::VoidTy,
false, false, false, false, CallingConv::C, false, false, false, false, false, CallingConv::C, false,
DAG.getExternalSymbol("abort", TLI.getPointerTy()), DAG.getExternalSymbol("abort", TLI.getPointerTy()),
@@ -5329,7 +5330,7 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
if (!Tmp2.getNode()) if (!Tmp2.getNode())
Tmp2 = DAG.getNode(ISD::SETCC, dl, Tmp2 = DAG.getNode(ISD::SETCC, dl,
TLI.getSetCCResultType(LHSHi.getValueType()), TLI.getSetCCResultType(LHSHi.getValueType()),
LHSHi, RHSHi,CC); LHSHi, RHSHi, CC);
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
@@ -5418,8 +5419,9 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
MVT DestVT, MVT DestVT,
DebugLoc dl) { DebugLoc dl) {
// Create the stack frame object. // Create the stack frame object.
unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( unsigned SrcAlign =
SrcOp.getValueType().getTypeForMVT()); TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
getTypeForMVT());
SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
@@ -5429,8 +5431,8 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
unsigned SlotSize = SlotVT.getSizeInBits(); unsigned SlotSize = SlotVT.getSizeInBits();
unsigned DestSize = DestVT.getSizeInBits(); unsigned DestSize = DestVT.getSizeInBits();
unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( unsigned DestAlign =
DestVT.getTypeForMVT()); TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
// Emit a store to the stack slot. Use a truncstore if the input value is // Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT. // later than DestVT.
@@ -5497,7 +5499,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
if (V.getOpcode() != ISD::UNDEF) if (V.getOpcode() != ISD::UNDEF)
isOnlyLowElement = false; isOnlyLowElement = false;
if (SplatValue != V) if (SplatValue != V)
SplatValue = SDValue(0,0); SplatValue = SDValue(0, 0);
// If this isn't a constant element or an undef, we can't use a constant // If this isn't a constant element or an undef, we can't use a constant
// pool load. // pool load.
@@ -5576,7 +5578,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
else else
Val2 = (++MI)->first; Val2 = (++MI)->first;
// If Val1 is an undef, make sure end ends up as Val2, to ensure that our // If Val1 is an undef, make sure it ends up as Val2, to ensure that our
// vector shuffle has the undef vector on the RHS. // vector shuffle has the undef vector on the RHS.
if (Val1.getOpcode() == ISD::UNDEF) if (Val1.getOpcode() == ISD::UNDEF)
std::swap(Val1, Val2); std::swap(Val1, Val2);
@@ -5671,7 +5673,7 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
/// smaller elements. If we can't find a way that is more efficient than a /// smaller elements. If we can't find a way that is more efficient than a
/// libcall on this target, return false. Otherwise, return true with the /// libcall on this target, return false. Otherwise, return true with the
/// low-parts expanded into Lo and Hi. /// low-parts expanded into Lo and Hi.
bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
SDValue &Lo, SDValue &Hi, SDValue &Lo, SDValue &Hi,
DebugLoc dl) { DebugLoc dl) {
assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
@@ -5698,7 +5700,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
} else if (Cst > NVTBits) { } else if (Cst > NVTBits) {
Lo = DAG.getConstant(0, NVT); Lo = DAG.getConstant(0, NVT);
Hi = DAG.getNode(ISD::SHL, dl, Hi = DAG.getNode(ISD::SHL, dl,
NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); NVT, InL, DAG.getConstant(Cst-NVTBits, ShTy));
} else if (Cst == NVTBits) { } else if (Cst == NVTBits) {
Lo = DAG.getConstant(0, NVT); Lo = DAG.getConstant(0, NVT);
Hi = InL; Hi = InL;
@@ -5716,7 +5718,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
Hi = DAG.getConstant(0, NVT); Hi = DAG.getConstant(0, NVT);
} else if (Cst > NVTBits) { } else if (Cst > NVTBits) {
Lo = DAG.getNode(ISD::SRL, dl, NVT, Lo = DAG.getNode(ISD::SRL, dl, NVT,
InH, DAG.getConstant(Cst-NVTBits,ShTy)); InH, DAG.getConstant(Cst-NVTBits, ShTy));
Hi = DAG.getConstant(0, NVT); Hi = DAG.getConstant(0, NVT);
} else if (Cst == NVTBits) { } else if (Cst == NVTBits) {
Lo = InH; Lo = InH;
@@ -5850,7 +5852,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
// Splice the libcall in wherever FindInputOutputChains tells us to. // Splice the libcall in wherever FindInputOutputChains tells us to.
const Type *RetTy = Node->getValueType(0).getTypeForMVT(); const Type *RetTy = Node->getValueType(0).getTypeForMVT();
std::pair<SDValue,SDValue> CallInfo = std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
CallingConv::C, false, Callee, Args, DAG, CallingConv::C, false, Callee, Args, DAG,
Node->getDebugLoc()); Node->getDebugLoc());
@@ -5916,8 +5918,7 @@ LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(), Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
Tmp1, DAG.getValueType(Op.getValueType())); Tmp1, DAG.getValueType(Op.getValueType()));
} else { } else {
Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Op.getValueType());
Op.getValueType());
} }
if (Result.getNode()) if (Result.getNode())
Result = DAG.UpdateNodeOperands(Result, Tmp1); Result = DAG.UpdateNodeOperands(Result, Tmp1);
@@ -6093,7 +6094,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
// set up Hi and Lo (into buffer) address based on endian // set up Hi and Lo (into buffer) address based on endian
SDValue Hi = StackSlot; SDValue Hi = StackSlot;
SDValue Lo = DAG.getNode(ISD::ADD, dl, SDValue Lo = DAG.getNode(ISD::ADD, dl,
TLI.getPointerTy(), StackSlot,WordOff); TLI.getPointerTy(), StackSlot, WordOff);
if (TLI.isLittleEndian()) if (TLI.isLittleEndian())
std::swap(Hi, Lo); std::swap(Hi, Lo);
@@ -6117,8 +6118,8 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
// FP constant to bias correct the final result // FP constant to bias correct the final result
SDValue Bias = DAG.getConstantFP(isSigned ? SDValue Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL) BitsToDouble(0x4330000080000000ULL) :
: BitsToDouble(0x4330000000000000ULL), BitsToDouble(0x4330000000000000ULL),
MVT::f64); MVT::f64);
// subtract the bias // subtract the bias
SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
@@ -6454,8 +6455,9 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
SDValue SrcLo, SrcHi, Src; SDValue SrcLo, SrcHi, Src;
ExpandOp(Op.getOperand(0), SrcLo, SrcHi); ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi); Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
SDValue Result = TLI.LowerOperation( SDValue Result =
DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG); TLI.LowerOperation(DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src,
Op.getOperand(1)), DAG);
assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
Lo = Result.getNode()->getOperand(0); Lo = Result.getNode()->getOperand(0);
Hi = Result.getNode()->getOperand(1); Hi = Result.getNode()->getOperand(1);
@@ -6829,7 +6831,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
SDValue Result = TLI.LowerOperation(Replace, DAG); SDValue Result = TLI.LowerOperation(Replace, DAG);
ExpandOp(Result.getValue(0), Lo, Hi); ExpandOp(Result.getValue(0), Lo, Hi);
// Remember that we legalized the chain. // Remember that we legalized the chain.
AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1))); AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Result.getValue(1)));
break; break;
} }
@@ -7423,8 +7425,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
MVT::ppcf128, Node->getOperand(0), MVT::ppcf128, Node->getOperand(0),
DAG.getConstant(0, MVT::i32), DAG.getConstant(0, MVT::i32),
DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi, DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
DAG.getConstantFP( DAG.getConstantFP
APFloat(APInt(128, 2, TwoE32)), (APFloat(APInt(128, 2, TwoE32)),
MVT::ppcf128)), MVT::ppcf128)),
Hi, Hi,
DAG.getCondCode(ISD::SETLT)), DAG.getCondCode(ISD::SETLT)),
@@ -7443,8 +7445,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
Node->getOperand(0), Node->getOperand(0),
DAG.getConstant(0, MVT::i64), DAG.getConstant(0, MVT::i64),
DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi, DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
DAG.getConstantFP( DAG.getConstantFP
APFloat(APInt(128, 2, TwoE64)), (APFloat(APInt(128, 2, TwoE64)),
MVT::ppcf128)), MVT::ppcf128)),
Hi, Hi,
DAG.getCondCode(ISD::SETLT)), DAG.getCondCode(ISD::SETLT)),
@@ -7804,8 +7806,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
// The input is a scalar or single-element vector. // The input is a scalar or single-element vector.
// Lower to a store/load so that it can be split. // Lower to a store/load so that it can be split.
// FIXME: this could be improved probably. // FIXME: this could be improved probably.
unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( unsigned LdAlign = TLI.getTargetData()->
Op.getValueType().getTypeForMVT()); getPrefTypeAlignment(Op.getValueType().getTypeForMVT());
SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex(); int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();