mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-23 05:29:23 +00:00
[AVX512] Added load/store instructions to Register2Memory opcode tables.
Added lowering tests for load/store. Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
e0243fb42d
commit
ec4188bad7
@ -377,7 +377,15 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
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{ X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
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// AVX-512 foldable instructions
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{ X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr, TB_FOLDED_STORE }
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{ X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
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{ X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
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{ X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
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{ X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
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{ X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
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{ X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
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{ X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
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{ X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
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{ X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE }
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};
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for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
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@ -601,10 +609,14 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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// AVX-512 foldable instructions
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{ X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
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{ X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
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{ X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
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{ X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
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{ X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
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{ X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
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{ X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
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{ X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
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{ X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
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{ X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
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{ X86::VPABSDZrr, X86::VPABSDZrm, 0 },
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{ X86::VPABSQZrr, X86::VPABSQZrm, 0 },
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@ -612,7 +624,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
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{ X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
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{ X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 },
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{ X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 },
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{ X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
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};
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for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
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@ -152,3 +152,296 @@ define void @test18(i8 * %addr, <8 x i64> %data) {
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store <8 x i64>%data, <8 x i64>* %vaddr, align 64
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ret void
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}
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; CHECK-LABEL: test19
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; CHECK: vmovdqu32
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; CHECK: ret
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define void @test19(i8 * %addr, <16 x i32> %data) {
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%vaddr = bitcast i8* %addr to <16 x i32>*
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store <16 x i32>%data, <16 x i32>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test20
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; CHECK: vmovdqa32
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; CHECK: ret
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define void @test20(i8 * %addr, <16 x i32> %data) {
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%vaddr = bitcast i8* %addr to <16 x i32>*
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store <16 x i32>%data, <16 x i32>* %vaddr, align 64
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ret void
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}
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; CHECK-LABEL: test21
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; CHECK: vmovdqa64
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; CHECK: ret
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define <8 x i64> @test21(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%res = load <8 x i64>* %vaddr, align 64
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test22
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; CHECK: vmovdqu64
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; CHECK: ret
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define void @test22(i8 * %addr, <8 x i64> %data) {
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%vaddr = bitcast i8* %addr to <8 x i64>*
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store <8 x i64>%data, <8 x i64>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test23
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; CHECK: vmovdqu64
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; CHECK: ret
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define <8 x i64> @test23(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%res = load <8 x i64>* %vaddr, align 1
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test24
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; CHECK: vmovapd
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; CHECK: ret
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define void @test24(i8 * %addr, <8 x double> %data) {
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%vaddr = bitcast i8* %addr to <8 x double>*
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store <8 x double>%data, <8 x double>* %vaddr, align 64
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ret void
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}
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; CHECK-LABEL: test25
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; CHECK: vmovapd
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; CHECK: ret
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define <8 x double> @test25(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x double>*
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%res = load <8 x double>* %vaddr, align 64
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ret <8 x double>%res
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}
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; CHECK-LABEL: test26
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; CHECK: vmovaps
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; CHECK: ret
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define void @test26(i8 * %addr, <16 x float> %data) {
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%vaddr = bitcast i8* %addr to <16 x float>*
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store <16 x float>%data, <16 x float>* %vaddr, align 64
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ret void
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}
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; CHECK-LABEL: test27
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; CHECK: vmovaps
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; CHECK: ret
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define <16 x float> @test27(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x float>*
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%res = load <16 x float>* %vaddr, align 64
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ret <16 x float>%res
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}
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; CHECK-LABEL: test28
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; CHECK: vmovupd
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; CHECK: ret
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define void @test28(i8 * %addr, <8 x double> %data) {
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%vaddr = bitcast i8* %addr to <8 x double>*
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store <8 x double>%data, <8 x double>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test29
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; CHECK: vmovupd
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; CHECK: ret
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define <8 x double> @test29(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <8 x double>*
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%res = load <8 x double>* %vaddr, align 1
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ret <8 x double>%res
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}
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; CHECK-LABEL: test30
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; CHECK: vmovups
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; CHECK: ret
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define void @test30(i8 * %addr, <16 x float> %data) {
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%vaddr = bitcast i8* %addr to <16 x float>*
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store <16 x float>%data, <16 x float>* %vaddr, align 1
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ret void
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}
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; CHECK-LABEL: test31
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; CHECK: vmovups
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; CHECK: ret
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define <16 x float> @test31(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x float>*
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%res = load <16 x float>* %vaddr, align 1
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ret <16 x float>%res
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}
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; CHECK-LABEL: test32
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; CHECK: vmovdqa32{{.*{%k[1-7]} }}
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; CHECK: ret
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define <16 x i32> @test32(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%r = load <16 x i32>* %vaddr, align 64
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%res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test33
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; CHECK: vmovdqu32{{.*{%k[1-7]} }}
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; CHECK: ret
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define <16 x i32> @test33(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%r = load <16 x i32>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test34
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; CHECK: vmovdqa32{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <16 x i32> @test34(i8 * %addr, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%r = load <16 x i32>* %vaddr, align 64
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%res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test35
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; CHECK: vmovdqu32{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <16 x i32> @test35(i8 * %addr, <16 x i32> %mask1) {
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%mask = icmp ne <16 x i32> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%r = load <16 x i32>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test36
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; CHECK: vmovdqa64{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x i64> @test36(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
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%mask = icmp ne <8 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%r = load <8 x i64>* %vaddr, align 64
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%res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test37
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; CHECK: vmovdqu64{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x i64> @test37(i8 * %addr, <8 x i64> %old, <8 x i64> %mask1) {
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%mask = icmp ne <8 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%r = load <8 x i64>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test38
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; CHECK: vmovdqa64{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x i64> @test38(i8 * %addr, <8 x i64> %mask1) {
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%mask = icmp ne <8 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%r = load <8 x i64>* %vaddr, align 64
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%res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test39
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; CHECK: vmovdqu64{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x i64> @test39(i8 * %addr, <8 x i64> %mask1) {
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%mask = icmp ne <8 x i64> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x i64>*
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%r = load <8 x i64>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer
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ret <8 x i64>%res
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}
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; CHECK-LABEL: test40
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; CHECK: vmovaps{{.*{%k[1-7]} }}
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; CHECK: ret
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define <16 x float> @test40(i8 * %addr, <16 x float> %old, <16 x float> %mask1) {
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%mask = fcmp one <16 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x float>*
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%r = load <16 x float>* %vaddr, align 64
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%res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old
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ret <16 x float>%res
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}
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; CHECK-LABEL: test41
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; CHECK: vmovups{{.*{%k[1-7]} }}
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; CHECK: ret
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define <16 x float> @test41(i8 * %addr, <16 x float> %old, <16 x float> %mask1) {
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%mask = fcmp one <16 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x float>*
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%r = load <16 x float>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old
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ret <16 x float>%res
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}
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; CHECK-LABEL: test42
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; CHECK: vmovaps{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <16 x float> @test42(i8 * %addr, <16 x float> %mask1) {
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%mask = fcmp one <16 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x float>*
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%r = load <16 x float>* %vaddr, align 64
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%res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer
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ret <16 x float>%res
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}
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; CHECK-LABEL: test43
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; CHECK: vmovups{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <16 x float> @test43(i8 * %addr, <16 x float> %mask1) {
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%mask = fcmp one <16 x float> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <16 x float>*
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%r = load <16 x float>* %vaddr, align 1
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%res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer
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ret <16 x float>%res
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}
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; CHECK-LABEL: test44
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; CHECK: vmovapd{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x double> @test44(i8 * %addr, <8 x double> %old, <8 x double> %mask1) {
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%mask = fcmp one <8 x double> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x double>*
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%r = load <8 x double>* %vaddr, align 64
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%res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old
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ret <8 x double>%res
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}
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; CHECK-LABEL: test45
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; CHECK: vmovupd{{.*{%k[1-7]} }}
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; CHECK: ret
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define <8 x double> @test45(i8 * %addr, <8 x double> %old, <8 x double> %mask1) {
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%mask = fcmp one <8 x double> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x double>*
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%r = load <8 x double>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old
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ret <8 x double>%res
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}
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; CHECK-LABEL: test46
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; CHECK: vmovapd{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x double> @test46(i8 * %addr, <8 x double> %mask1) {
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%mask = fcmp one <8 x double> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x double>*
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%r = load <8 x double>* %vaddr, align 64
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%res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer
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ret <8 x double>%res
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}
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; CHECK-LABEL: test47
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; CHECK: vmovupd{{.*{%k[1-7]} {z} }}
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; CHECK: ret
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define <8 x double> @test47(i8 * %addr, <8 x double> %mask1) {
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%mask = fcmp one <8 x double> %mask1, zeroinitializer
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%vaddr = bitcast i8* %addr to <8 x double>*
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%r = load <8 x double>* %vaddr, align 1
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%res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer
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ret <8 x double>%res
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}
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