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[mips][microMIPSr6] Implement initial subtarget support

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Differential Revision: http://reviews.llvm.org/D8386


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek
2015-04-20 12:23:06 +00:00
parent 14fc08301c
commit ec47ed84d2
4 changed files with 11 additions and 0 deletions
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4
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@@ -115,6 +115,10 @@ bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
return STI.getFeatureBits() & Mips::FeatureMicroMips; return STI.getFeatureBits() & Mips::FeatureMicroMips;
} }
bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
return STI.getFeatureBits() & Mips::FeatureMips32r6;
}
void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
OS << (char)C; OS << (char)C;
} }

1
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
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@@ -38,6 +38,7 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
bool IsLittleEndian; bool IsLittleEndian;
bool isMicroMips(const MCSubtargetInfo &STI) const; bool isMicroMips(const MCSubtargetInfo &STI) const;
bool isMips32r6(const MCSubtargetInfo &STI) const;
public: public:
MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)

5
lib/Target/Mips/MipsInstrInfo.td
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@@ -182,6 +182,8 @@ def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
AssemblerPredicate<"FeatureMips64r6">; AssemblerPredicate<"FeatureMips64r6">;
def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">, def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
AssemblerPredicate<"!FeatureMips64r6">; AssemblerPredicate<"!FeatureMips64r6">;
def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
AssemblerPredicate<"FeatureMips16">; AssemblerPredicate<"FeatureMips16">;
def HasCnMips : Predicate<"Subtarget->hasCnMips()">, def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
@@ -247,6 +249,9 @@ class ISA_MIPS64_NOT_64R6 {
class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; } class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; } class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; } class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
class ISA_MICROMIPS32R6 {
list<Predicate> InsnPredicates = [HasMicroMips32r6];
}
// The portions of MIPS-III that were also added to MIPS32 // The portions of MIPS-III that were also added to MIPS32
class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; } class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }

1
lib/Target/Mips/MipsSubtarget.h
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@@ -225,6 +225,7 @@ public:
return inMips16Mode() && InMips16HardFloat; return inMips16Mode() && InMips16HardFloat;
} }
bool inMicroMipsMode() const { return InMicroMipsMode; } bool inMicroMipsMode() const { return InMicroMipsMode; }
bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
bool hasDSP() const { return HasDSP; } bool hasDSP() const { return HasDSP; }
bool hasDSPR2() const { return HasDSPR2; } bool hasDSPR2() const { return HasDSPR2; }
bool hasMSA() const { return HasMSA; } bool hasMSA() const { return HasMSA; }