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Handle MOV32r0 in expandPostRAPseudo instead of MCInst lowering. No functional change intended.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198254 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-12-31 03:05:38 +00:00
parent ad5e4b9476
commit ec62c1ae99
3 changed files with 4 additions and 10 deletions
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4
lib/Target/X86/X86InstrCompiler.td
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@ -222,8 +222,8 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
// FIXME: remove when we can teach regalloc that xor reg, reg is ok. // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
// FIXME: Set encoding to pseudo. // FIXME: Set encoding to pseudo.
let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
isCodeGenOnly = 1 in isPseudo = 1 in
def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "", def MOV32r0 : I<0x31, Pseudo, (outs GR32:$dst), (ins), "",
[(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>; [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
// Other widths can also make use of the 32-bit xor, which may have a smaller // Other widths can also make use of the 32-bit xor, which may have a smaller

2
lib/Target/X86/X86InstrInfo.cpp
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@ -3854,6 +3854,8 @@ bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
case X86::MOV32r0:
return Expand2AddrUndef(MIB, get(X86::XOR32rr));
case X86::SETB_C8r: case X86::SETB_C8r:
return Expand2AddrUndef(MIB, get(X86::SBB8rr)); return Expand2AddrUndef(MIB, get(X86::SBB8rr));
case X86::SETB_C16r: case X86::SETB_C16r:

8
lib/Target/X86/X86MCInstLower.cpp
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@ -232,13 +232,6 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
} }
/// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
OutMI.setOpcode(NewOpc);
OutMI.addOperand(OutMI.getOperand(0));
OutMI.addOperand(OutMI.getOperand(0));
}
/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
/// a short fixed-register form. /// a short fixed-register form.
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
@ -395,7 +388,6 @@ ReSimplify:
assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
"LEA has segment specified!"); "LEA has segment specified!");
break; break;
case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
case X86::MOV32ri64: case X86::MOV32ri64:
OutMI.setOpcode(X86::MOV32ri); OutMI.setOpcode(X86::MOV32ri);