mirror of
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Mips specific llvm assembler support for ALU instructions. This includes
register support. Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163268 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jack Carter
parent
2f1d815479
commit
ec65be84cd
@ -8,20 +8,28 @@
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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namespace {
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class MipsAsmParser : public MCTargetAsmParser {
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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#define GET_ASSEMBLER_HEADER
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#include "MipsGenAsmMatcher.inc"
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@ -36,17 +44,42 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool ParseDirective(AsmToken DirectiveID);
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OperandMatchResultTy parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
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MipsAsmParser::OperandMatchResultTy
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parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
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unsigned getMCInstOperandNum(unsigned Kind, MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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unsigned OperandNum, unsigned &NumMCOperands);
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unsigned
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getMCInstOperandNum(unsigned Kind, MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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unsigned OperandNum, unsigned &NumMCOperands);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
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StringRef Mnemonic);
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int tryParseRegister(StringRef Mnemonic);
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bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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StringRef Mnemonic);
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bool isMips64() const {
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return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
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}
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int matchRegisterName(StringRef Symbol);
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int matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic);
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unsigned getReg(int RC,int RegNo);
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public:
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MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
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: MCTargetAsmParser() {
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: MCTargetAsmParser(), STI(sti), Parser(parser) {
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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};
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}
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@ -55,6 +88,7 @@ namespace {
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/// MipsOperand - Instances of this class represent a parsed Mips machine
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/// instruction.
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class MipsOperand : public MCParsedAsmOperand {
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enum KindTy {
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k_CondCode,
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k_CoprocNum,
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@ -66,16 +100,46 @@ class MipsOperand : public MCParsedAsmOperand {
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} Kind;
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MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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union {
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNum;
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} Reg;
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struct {
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const MCExpr *Val;
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} Imm;
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};
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SMLoc StartLoc, EndLoc;
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public:
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void addRegOperands(MCInst &Inst, unsigned N) const {
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llvm_unreachable("unimplemented!");
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const{
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llvm_unreachable("unimplemented!");
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// Add as immediate when possible. Null MCExpr = 0.
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if (Expr == 0)
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Inst.addOperand(MCOperand::CreateImm(0));
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else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::CreateExpr(Expr));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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llvm_unreachable("unimplemented!");
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assert(N == 1 && "Invalid number of operands!");
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const MCExpr *Expr = getImm();
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addExpr(Inst,Expr);
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}
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void addMemOperands(MCInst &Inst, unsigned N) const {
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llvm_unreachable("unimplemented!");
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}
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@ -87,14 +151,49 @@ public:
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StringRef getToken() const {
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assert(Kind == k_Token && "Invalid access!");
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return "";
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return StringRef(Tok.Data, Tok.Length);
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}
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unsigned getReg() const {
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assert((Kind == k_Register) && "Invalid access!");
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return 0;
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return Reg.RegNum;
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}
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const MCExpr *getImm() const {
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assert((Kind == k_Immediate) && "Invalid access!");
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return Imm.Val;
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}
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static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
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MipsOperand *Op = new MipsOperand(k_Token);
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Op->Tok.Data = Str.data();
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Op->Tok.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
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MipsOperand *Op = new MipsOperand(k_Register);
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Op->Reg.RegNum = RegNum;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
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MipsOperand *Op = new MipsOperand(k_Immediate);
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Op->Imm.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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virtual void print(raw_ostream &OS) const {
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llvm_unreachable("unimplemented!");
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}
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@ -117,18 +216,265 @@ bool MipsAsmParser::
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MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out) {
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MCInst Inst;
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unsigned ErrorInfo;
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unsigned Kind;
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unsigned MatchResult = MatchInstructionImpl(Operands, Kind, Inst, ErrorInfo);
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switch (MatchResult) {
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default: break;
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case Match_Success: {
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Inst.setLoc(IDLoc);
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Out.EmitInstruction(Inst);
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return false;
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}
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case Match_MissingFeature:
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Error(IDLoc, "instruction requires a CPU feature not currently enabled");
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return true;
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case Match_InvalidOperand: {
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SMLoc ErrorLoc = IDLoc;
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if (ErrorInfo != ~0U) {
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if (ErrorInfo >= Operands.size())
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return Error(IDLoc, "too few operands for instruction");
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ErrorLoc = ((MipsOperand*)Operands[ErrorInfo])->getStartLoc();
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if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
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}
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return Error(ErrorLoc, "invalid operand for instruction");
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}
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case Match_MnemonicFail:
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return Error(IDLoc, "invalid instruction");
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}
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return true;
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}
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int MipsAsmParser::matchRegisterName(StringRef Name) {
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int CC = StringSwitch<unsigned>(Name)
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.Case("zero", Mips::ZERO)
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.Case("a0", Mips::A0)
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.Case("a1", Mips::A1)
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.Case("a2", Mips::A2)
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.Case("a3", Mips::A3)
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.Case("v0", Mips::V0)
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.Case("v1", Mips::V1)
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.Case("s0", Mips::S0)
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.Case("s1", Mips::S1)
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.Case("s2", Mips::S2)
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.Case("s3", Mips::S3)
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.Case("s4", Mips::S4)
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.Case("s5", Mips::S5)
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.Case("s6", Mips::S6)
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.Case("s7", Mips::S7)
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.Case("k0", Mips::K0)
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.Case("k1", Mips::K1)
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.Case("sp", Mips::SP)
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.Case("fp", Mips::FP)
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.Case("gp", Mips::GP)
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.Case("ra", Mips::RA)
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.Case("t0", Mips::T0)
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.Case("t1", Mips::T1)
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.Case("t2", Mips::T2)
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.Case("t3", Mips::T3)
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.Case("t4", Mips::T4)
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.Case("t5", Mips::T5)
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.Case("t6", Mips::T6)
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.Case("t7", Mips::T7)
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.Case("t8", Mips::T8)
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.Case("t9", Mips::T9)
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.Case("at", Mips::AT)
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.Case("fcc0", Mips::FCC0)
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.Default(-1);
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if (CC != -1) {
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//64 bit register in Mips are following 32 bit definitions.
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if (isMips64())
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CC++;
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return CC;
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}
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return -1;
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}
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unsigned MipsAsmParser::getReg(int RC,int RegNo){
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return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
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}
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int MipsAsmParser::matchRegisterByNumber(unsigned RegNum,StringRef Mnemonic) {
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if (Mnemonic.lower() == "rdhwr") {
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//at the moment only hwreg29 is supported
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if (RegNum != 29)
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return -1;
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return Mips::HWR29;
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}
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if (RegNum > 31)
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return -1;
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return getReg(Mips::CPURegsRegClassID,RegNum);
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}
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int MipsAsmParser::tryParseRegister(StringRef Mnemonic) {
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const AsmToken &Tok = Parser.getTok();
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int RegNum = -1;
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if (Tok.is(AsmToken::Identifier)) {
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std::string lowerCase = Tok.getString().lower();
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RegNum = matchRegisterName(lowerCase);
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} else if (Tok.is(AsmToken::Integer))
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RegNum = matchRegisterByNumber(static_cast<unsigned> (Tok.getIntVal()),
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Mnemonic.lower());
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return RegNum;
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}
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bool MipsAsmParser::
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ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
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tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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StringRef Mnemonic){
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SMLoc S = Parser.getTok().getLoc();
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int RegNo = -1;
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RegNo = tryParseRegister(Mnemonic);
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if (RegNo == -1)
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return true;
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Operands.push_back(MipsOperand::CreateReg(RegNo, S,
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Parser.getTok().getLoc()));
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Parser.Lex(); // Eat register token.
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return false;
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}
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bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
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StringRef Mnemonic) {
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//Check if the current operand has a custom associated parser, if so, try to
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//custom parse the operand, or fallback to the general approach.
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OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
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if (ResTy == MatchOperand_Success)
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return false;
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// If there wasn't a custom match, try the generic matcher below. Otherwise,
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// there was a match, but an error occurred, in which case, just return that
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// the operand parsing failed.
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if (ResTy == MatchOperand_ParseFail)
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return true;
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switch (getLexer().getKind()) {
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default:
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Error(Parser.getTok().getLoc(), "unexpected token in operand");
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return true;
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case AsmToken::Dollar: {
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//parse register
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SMLoc S = Parser.getTok().getLoc();
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Parser.Lex(); // Eat dollar token.
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//parse register operand
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if (!tryParseRegisterOperand(Operands,Mnemonic)) {
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if (getLexer().is(AsmToken::LParen)) {
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//check if it is indexed addressing operand
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Operands.push_back(MipsOperand::CreateToken("(", S));
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Parser.Lex(); //eat parenthesis
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if (getLexer().isNot(AsmToken::Dollar))
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return true;
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Parser.Lex(); //eat dollar
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if (tryParseRegisterOperand(Operands,Mnemonic))
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return true;
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if (!getLexer().is(AsmToken::RParen))
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return true;
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S = Parser.getTok().getLoc();
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Operands.push_back(MipsOperand::CreateToken(")", S));
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Parser.Lex();
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}
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return false;
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}
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//maybe it is a symbol reference
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StringRef Identifier;
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if (Parser.ParseIdentifier(Identifier))
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return true;
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SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
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StringRef Id = StringRef("$" + Identifier.str());
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MCSymbol *Sym = getContext().GetOrCreateSymbol(Id);
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// Otherwise create a symbol ref.
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const MCExpr *Res = MCSymbolRefExpr::Create(Sym,
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MCSymbolRefExpr::VK_None,
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getContext());
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Operands.push_back(MipsOperand::CreateImm(Res, S, E));
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return false;
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}
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case AsmToken::Identifier:
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case AsmToken::LParen:
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case AsmToken::Minus:
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case AsmToken::Plus:
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case AsmToken::Integer:
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case AsmToken::String: {
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// quoted label names
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const MCExpr *IdVal;
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SMLoc S = Parser.getTok().getLoc();
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if (getParser().ParseExpression(IdVal))
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return true;
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SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
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Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
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return false;
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}
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}//switch(getLexer().getKind())
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return true;
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}
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bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
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SMLoc &EndLoc) {
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StartLoc = Parser.getTok().getLoc();
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RegNo = tryParseRegister("");
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EndLoc = Parser.getTok().getLoc();
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return (RegNo == (unsigned)-1);
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}
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MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
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SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
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return MatchOperand_Success;
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}
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bool MipsAsmParser::
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ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return true;
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//first operand is a instruction mnemonic
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Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
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// Read the remaining operands.
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Read the first operand.
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if (ParseOperand(Operands, Name)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.EatToEndOfStatement();
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return Error(Loc, "unexpected token in argument list");
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}
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while (getLexer().is(AsmToken::Comma) ) {
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Parser.Lex(); // Eat the comma.
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// Parse and remember the operand.
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if (ParseOperand(Operands, Name)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.EatToEndOfStatement();
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return Error(Loc, "unexpected token in argument list");
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}
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}
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}
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.EatToEndOfStatement();
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return Error(Loc, "unexpected token in argument list");
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}
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Parser.Lex(); // Consume the EndOfStatement
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return false;
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}
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bool MipsAsmParser::
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@ -136,14 +482,13 @@ ParseDirective(AsmToken DirectiveID) {
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return true;
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}
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MipsAsmParser::OperandMatchResultTy MipsAsmParser::
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parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&) {
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return MatchOperand_ParseFail;
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}
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extern "C" void LLVMInitializeMipsAsmParser() {
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RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
|
||||
RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
|
||||
RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
|
||||
RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
|
||||
}
|
||||
|
||||
#define GET_REGISTER_MATCHER
|
||||
#define GET_MATCHER_IMPLEMENTATION
|
||||
#include "MipsGenAsmMatcher.inc"
|
||||
|
||||
81
test/MC/Mips/mips-alu-instructions.s
Normal file
81
test/MC/Mips/mips-alu-instructions.s
Normal file
@ -0,0 +1,81 @@
|
||||
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
|
||||
# Check that the assembler can handle the documented syntax
|
||||
# for arithmetic and logical instructions.
|
||||
# CHECK: .section __TEXT,__text,regular,pure_instructions
|
||||
#------------------------------------------------------------------------------
|
||||
# Logical instructions
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK: and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00]
|
||||
# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
|
||||
# CHECK: clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70]
|
||||
# CHECK: clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70]
|
||||
# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
|
||||
# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
|
||||
# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
|
||||
# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
|
||||
# CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
|
||||
# CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
|
||||
# CHECK: sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00]
|
||||
# CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
|
||||
# CHECK: slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00]
|
||||
# CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
|
||||
# CHECK: sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c]
|
||||
# CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
|
||||
# CHECK: sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
|
||||
# CHECK: srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00]
|
||||
# CHECK: srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00]
|
||||
# CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
|
||||
# CHECK: xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00]
|
||||
# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
|
||||
# CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
|
||||
and $9, $6, $7
|
||||
andi $9, $6, 17767
|
||||
clo $6, $7
|
||||
clz $6, $7
|
||||
ins $19, $9, 6,7
|
||||
nor $9, $6, $7
|
||||
or $3, $3, $5
|
||||
ori $9, $6, 17767
|
||||
rotr $9, $6, 7
|
||||
rotrv $9, $6, $7
|
||||
sll $4, $3, 7
|
||||
sllv $2, $3, $5
|
||||
slt $3, $3, $5
|
||||
slti $3, $3, 103
|
||||
sltiu $3, $3, 103
|
||||
sltu $3, $3, $5
|
||||
sra $4, $3, 7
|
||||
srav $2, $3, $5
|
||||
srl $4, $3, 7
|
||||
srlv $2, $3, $5
|
||||
xor $3, $3, $5
|
||||
xori $9, $6, 17767
|
||||
wsbh $6, $7
|
||||
#------------------------------------------------------------------------------
|
||||
# Arithmetic instructions
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
# CHECK: add $9, $6, $7 # encoding: [0x20,0x48,0xc7,0x00]
|
||||
# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
|
||||
# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
|
||||
# CHECK: addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00]
|
||||
# CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
|
||||
# CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70]
|
||||
# CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
|
||||
# CHECK: msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70]
|
||||
# CHECK: mult $3, $5 # encoding: [0x18,0x00,0x65,0x00]
|
||||
# CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
|
||||
# CHECK: sub $9, $6, $7 # encoding: [0x22,0x48,0xc7,0x00]
|
||||
# CHECK: subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00]
|
||||
add $9,$6,$7
|
||||
addi $9,$6,17767
|
||||
addiu $9,$6,-15001
|
||||
addu $9,$6,$7
|
||||
madd $6,$7
|
||||
maddu $6,$7
|
||||
msub $6,$7
|
||||
msubu $6,$7
|
||||
mult $3,$5
|
||||
multu $3,$5
|
||||
sub $9,$6,$7
|
||||
subu $4,$3,$5
|
||||
Loading…
Reference in New Issue
Block a user