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https://github.com/c64scene-ar/llvm-6502.git
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* Added intelligence to X86 LEA addressing mode matching routine so it returns
false if the match is not profitable. e.g. leal 1(%eax), %eax. * Added patterns for X86 integer loads and LEA32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24635 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
0fc7198890
commit
ec693f77c0
@ -36,6 +36,7 @@ namespace {
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enum {
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RegBase,
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FrameIndexBase,
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ConstantPoolBase
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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@ -94,8 +95,11 @@ namespace {
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private:
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SDOperand Select(SDOperand N);
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void SelectAddress(SDOperand N, X86ISelAddressMode &AM);
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bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
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bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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/// getI8Imm - Return a target constant with the specified value, of type
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/// i8.
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@ -130,23 +134,6 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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ScheduleAndEmitDAG(DAG);
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}
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/// SelectAddress - Pattern match the maximal addressing mode for this node.
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void X86DAGToDAGISel::SelectAddress(SDOperand N, X86ISelAddressMode &AM) {
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MatchAddress(N, AM);
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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if (AM.Base.Reg.Val)
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AM.Base.Reg = Select(AM.Base.Reg);
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else
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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}
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if (!AM.IndexReg.Val) {
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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} else {
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AM.IndexReg = Select(AM.IndexReg);
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}
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}
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/// FIXME: copied from X86ISelPattern.cpp
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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@ -161,6 +148,17 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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return false;
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}
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break;
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case ISD::ConstantPool:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N)) {
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AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
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AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32);
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return false;
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}
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}
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break;
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case ISD::GlobalAddress:
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if (AM.GV == 0) {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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@ -177,9 +175,11 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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}
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}
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break;
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case ISD::Constant:
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AM.Disp += cast<ConstantSDNode>(N)->getValue();
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return false;
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case ISD::SHL:
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if (AM.IndexReg.Val == 0 && AM.Scale == 1)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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@ -204,6 +204,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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}
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}
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break;
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case ISD::MUL:
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// X*[3,5,9] -> X+X*[2,4,8]
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if (AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
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@ -266,6 +267,67 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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return false;
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}
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/// SelectAddr - returns true if it is able pattern match an addressing mode.
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/// It returns the operands which make up the maximal addressing mode it can
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/// match by reference.
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bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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X86ISelAddressMode AM;
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if (!MatchAddress(N, AM)) {
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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if (AM.Base.Reg.Val)
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AM.Base.Reg = Select(AM.Base.Reg);
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else
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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}
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if (AM.IndexReg.Val)
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AM.IndexReg = Select(AM.IndexReg);
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else
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
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CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
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Scale = getI8Imm (AM.Scale);
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Index = AM.IndexReg;
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Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: getI32Imm(AM.Disp);
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return true;
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}
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return false;
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}
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static bool isRegister0(SDOperand Op)
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{
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if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
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return (R->getReg() == 0);
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return false;
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}
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/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
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/// mode it matches can be cost effectively emitted as an LEA instruction.
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/// For X86, it always is unless it's just a (Reg + const).
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bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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if (SelectAddr(N, Base, Scale, Index, Disp)) {
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if (!isRegister0(Base)) {
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unsigned Complexity = 0;
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if ((unsigned)cast<ConstantSDNode>(Scale)->getValue() > 1)
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Complexity++;
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if (!isRegister0(Index))
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Complexity++;
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Disp)) {
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if (!CN->isNullValue()) Complexity++;
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} else {
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Complexity++;
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}
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return (Complexity > 1);
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}
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return true;
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} else {
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return false;
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}
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}
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SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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MVT::ValueType OpVT = N->getValueType(0);
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@ -326,51 +388,9 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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Chain);
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}
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case ISD::LOAD: {
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switch (OpVT) {
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default: assert(0 && "Cannot load this type!");
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case MVT::i1:
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case MVT::i8: Opc = X86::MOV8rm; break;
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case MVT::i16: Opc = X86::MOV16rm; break;
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case MVT::i32: Opc = X86::MOV32rm; break;
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case MVT::f32: Opc = X86::MOVSSrm; break;
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case MVT::f64: Opc = X86::FLD64m; ContainsFPCode = true; break;
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}
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N->getOperand(1))){
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unsigned CPIdx = BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get());
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// ???
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assert(0 && "Can't handle load from constant pool!");
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} else {
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X86ISelAddressMode AM;
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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SelectAddress(N->getOperand(1), AM);
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SDOperand Scale = getI8Imm (AM.Scale);
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SDOperand Disp = AM.GV
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? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: getI32Imm(AM.Disp);
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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return CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
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AM.Base.Reg, Scale, AM.IndexReg, Disp,
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Chain)
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.getValue(Op.ResNo);
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} else {
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SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
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return CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
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Base, Scale, AM.IndexReg, Disp, Chain)
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.getValue(Op.ResNo);
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}
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}
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}
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case ISD::STORE: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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SDOperand Tmp1 = Select(N->getOperand(1));
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X86ISelAddressMode AM;
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SelectAddress(N->getOperand(2), AM);
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Opc = 0;
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
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switch (CN->getValueType(0)) {
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@ -394,19 +414,11 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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}
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}
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SDOperand Scale = getI8Imm (AM.Scale);
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SDOperand Disp = AM.GV
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? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: getI32Imm(AM.Disp);
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
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AM.Base.Reg, Scale, AM.IndexReg, Disp, Tmp1,
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Chain);
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} else {
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SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
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return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
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Base, Scale, AM.IndexReg, Disp, Tmp1, Chain);
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}
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SDOperand Base, Scale, Index, Disp;
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SelectAddr(N->getOperand(2), Base, Scale, Index, Disp);
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return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
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Base, Scale, Index, Disp, Tmp1, Chain)
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.getValue(Op.ResNo);
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}
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}
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@ -21,13 +21,13 @@ class X86MemOperand<ValueType Ty, string printMethod> : Operand<Ty> {
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let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
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}
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def i8mem : X86MemOperand<i8, "printi8mem">;
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def i16mem : X86MemOperand<i16, "printi16mem">;
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def i8mem : X86MemOperand<i32, "printi8mem">;
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def i16mem : X86MemOperand<i32, "printi16mem">;
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def i32mem : X86MemOperand<i32, "printi32mem">;
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def i64mem : X86MemOperand<i64, "printi64mem">;
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def f32mem : X86MemOperand<f32, "printf32mem">;
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def f64mem : X86MemOperand<f64, "printf64mem">;
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def f80mem : X86MemOperand<f80, "printf80mem">;
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def i64mem : X86MemOperand<i32, "printi64mem">;
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def f32mem : X86MemOperand<i32, "printf32mem">;
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def f64mem : X86MemOperand<i32, "printf64mem">;
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def f80mem : X86MemOperand<i32, "printf80mem">;
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def SSECC : Operand<i8> {
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let PrintMethod = "printSSECC";
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@ -46,6 +46,10 @@ let PrintMethod = "printCallOperand" in
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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// Define X86 specific addressing mode.
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def addr : ComplexPattern<4, "SelectAddr", []>;
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def leaaddr : ComplexPattern<4, "SelectLEAAddr", [add]>;
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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@ -151,7 +155,6 @@ def immZExt8 : PatLeaf<(imm), [{
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return (unsigned)N->getValue() == (unsigned char)N->getValue();
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}]>;
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//===----------------------------------------------------------------------===//
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// Instruction templates...
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@ -297,7 +300,8 @@ def LEA16r : I<0x8D, MRMSrcMem,
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"lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
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def LEA32r : I<0x8D, MRMSrcMem,
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(ops R32:$dst, i32mem:$src),
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"lea{l} {$src|$dst}, {$dst|$src}", []>;
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"lea{l} {$src|$dst}, {$dst|$src}",
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[(set R32:$dst, leaaddr:$src)]>;
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def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", []>,
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@ -381,11 +385,14 @@ def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
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"mov{l} {$src, $dst|$dst, $src}", []>;
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def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
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"mov{b} {$src, $dst|$dst, $src}", []>;
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"mov{b} {$src, $dst|$dst, $src}",
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[(set R8:$dst, (load addr:$src))]>;
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def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src),
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"mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
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"mov{w} {$src, $dst|$dst, $src}",
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[(set R16:$dst, (load addr:$src))]>, OpSize;
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def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
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"mov{l} {$src, $dst|$dst, $src}", []>;
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"mov{l} {$src, $dst|$dst, $src}",
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[(set R32:$dst, (load addr:$src))]>;
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def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
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"mov{b} {$src, $dst|$dst, $src}", []>;
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