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https://github.com/c64scene-ar/llvm-6502.git
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Adding more assignment of ordering to SDNodes. This time in the "call" and
generic copy functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91872 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -144,15 +144,15 @@ namespace {
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/// this value and returns the result as a ValueVTs value. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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SDValue &Chain, SDValue *Flag) const;
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SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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SDValue &Chain, SDValue *Flag) const;
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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/// specified value into the registers specified by this object. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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SDValue &Chain, SDValue *Flag) const;
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unsigned Order, SDValue &Chain, SDValue *Flag) const;
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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/// operand list. This adds the code marker, matching input operand index
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@ -720,10 +720,8 @@ SDValue SelectionDAGBuilder::getValue(const Value *V) {
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RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
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SDValue Chain = DAG.getEntryNode();
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SDValue Res = RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return Res;
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return RFV.getCopyFromRegs(DAG, getCurDebugLoc(),
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SDNodeOrder, Chain, NULL);
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}
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/// Get the EVTs and ArgFlags collections that represent the return type
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@ -5046,8 +5044,11 @@ void SelectionDAGBuilder::visitCall(CallInst &I) {
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I.getType() == I.getOperand(2)->getType()) {
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SDValue LHS = getValue(I.getOperand(1));
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SDValue RHS = getValue(I.getOperand(2));
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setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
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LHS.getValueType(), LHS, RHS));
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SDValue Res = DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
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LHS.getValueType(), LHS, RHS);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return;
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}
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} else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
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@ -5055,8 +5056,11 @@ void SelectionDAGBuilder::visitCall(CallInst &I) {
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I.getOperand(1)->getType()->isFloatingPoint() &&
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I.getType() == I.getOperand(1)->getType()) {
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SDValue Tmp = getValue(I.getOperand(1));
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setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
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Tmp.getValueType(), Tmp));
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SDValue Res = DAG.getNode(ISD::FABS, getCurDebugLoc(),
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Tmp.getValueType(), Tmp);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return;
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}
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} else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
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@ -5065,8 +5069,11 @@ void SelectionDAGBuilder::visitCall(CallInst &I) {
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I.getType() == I.getOperand(1)->getType() &&
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I.onlyReadsMemory()) {
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SDValue Tmp = getValue(I.getOperand(1));
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setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
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Tmp.getValueType(), Tmp));
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SDValue Res = DAG.getNode(ISD::FSIN, getCurDebugLoc(),
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Tmp.getValueType(), Tmp);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return;
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}
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} else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
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@ -5075,8 +5082,11 @@ void SelectionDAGBuilder::visitCall(CallInst &I) {
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I.getType() == I.getOperand(1)->getType() &&
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I.onlyReadsMemory()) {
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SDValue Tmp = getValue(I.getOperand(1));
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setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
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Tmp.getValueType(), Tmp));
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SDValue Res = DAG.getNode(ISD::FCOS, getCurDebugLoc(),
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Tmp.getValueType(), Tmp);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return;
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}
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} else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
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@ -5085,8 +5095,11 @@ void SelectionDAGBuilder::visitCall(CallInst &I) {
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I.getType() == I.getOperand(1)->getType() &&
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I.onlyReadsMemory()) {
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SDValue Tmp = getValue(I.getOperand(1));
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setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
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Tmp.getValueType(), Tmp));
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SDValue Res = DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
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Tmp.getValueType(), Tmp);
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setValue(&I, Res);
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
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return;
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}
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}
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@ -5102,6 +5115,9 @@ void SelectionDAGBuilder::visitCall(CallInst &I) {
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else
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Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
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if (DisableScheduling)
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DAG.AssignOrdering(Callee.getNode(), SDNodeOrder);
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// Check if we can potentially perform a tail call. More detailed
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// checking is be done within LowerCallTo, after more information
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// about the call is known.
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@ -5110,13 +5126,12 @@ void SelectionDAGBuilder::visitCall(CallInst &I) {
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LowerCallTo(&I, Callee, isTailCall);
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}
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/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
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/// this value and returns the result as a ValueVT value. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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SDValue &Chain,
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unsigned Order, SDValue &Chain,
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SDValue *Flag) const {
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// Assemble the legal parts into the final values.
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SmallVector<SDValue, 4> Values(ValueVTs.size());
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@ -5130,14 +5145,18 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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Parts.resize(NumRegs);
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for (unsigned i = 0; i != NumRegs; ++i) {
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SDValue P;
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if (Flag == 0)
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if (Flag == 0) {
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P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
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else {
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} else {
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P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
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*Flag = P.getValue(2);
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}
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Chain = P.getValue(1);
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if (DisableScheduling)
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DAG.AssignOrdering(P.getNode(), Order);
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// If the source register was virtual and if we know something about it,
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// add an assert node.
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if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
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@ -5176,6 +5195,8 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
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RegisterVT, P, DAG.getValueType(FromVT));
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if (DisableScheduling)
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DAG.AssignOrdering(P.getNode(), Order);
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}
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}
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}
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@ -5185,13 +5206,18 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
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NumRegs, RegisterVT, ValueVT);
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if (DisableScheduling)
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DAG.AssignOrdering(Values[Value].getNode(), Order);
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Part += NumRegs;
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Parts.clear();
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}
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return DAG.getNode(ISD::MERGE_VALUES, dl,
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DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
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&Values[0], ValueVTs.size());
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SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
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DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
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&Values[0], ValueVTs.size());
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if (DisableScheduling)
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DAG.AssignOrdering(Res.getNode(), Order);
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return Res;
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}
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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@ -5199,7 +5225,8 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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SDValue &Chain, SDValue *Flag) const {
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unsigned Order, SDValue &Chain,
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SDValue *Flag) const {
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// Get the list of the values's legal parts.
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unsigned NumRegs = Regs.size();
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SmallVector<SDValue, 8> Parts(NumRegs);
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@ -5217,13 +5244,17 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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SmallVector<SDValue, 8> Chains(NumRegs);
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for (unsigned i = 0; i != NumRegs; ++i) {
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SDValue Part;
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if (Flag == 0)
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if (Flag == 0) {
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Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
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else {
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} else {
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Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
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*Flag = Part.getValue(1);
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}
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Chains[i] = Part.getValue(0);
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if (DisableScheduling)
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DAG.AssignOrdering(Part.getNode(), Order);
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}
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if (NumRegs == 1 || Flag)
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@ -5240,6 +5271,9 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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Chain = Chains[NumRegs-1];
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else
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
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if (DisableScheduling)
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DAG.AssignOrdering(Chain.getNode(), Order);
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}
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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@ -5876,7 +5910,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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// Use the produced MatchedRegs object to
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MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
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Chain, &Flag);
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SDNodeOrder, Chain, &Flag);
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MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
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true, OpInfo.getMatchedOperand(),
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DAG, AsmNodeOperands);
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@ -5939,7 +5973,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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}
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OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
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Chain, &Flag);
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SDNodeOrder, Chain, &Flag);
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OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
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DAG, AsmNodeOperands);
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@ -5969,7 +6003,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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// and set it as the value of the call.
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if (!RetValRegs.Regs.empty()) {
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SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
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Chain, &Flag);
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SDNodeOrder, Chain, &Flag);
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// FIXME: Why don't we do this for inline asms with MRVs?
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if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
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@ -6009,7 +6043,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
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Value *Ptr = IndirectStoresToEmit[i].second;
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SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
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Chain, &Flag);
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SDNodeOrder, Chain, &Flag);
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StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
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}
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@ -6251,7 +6285,7 @@ void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
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RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
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SDValue Chain = DAG.getEntryNode();
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RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
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RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), SDNodeOrder, Chain, 0);
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PendingExports.push_back(Chain);
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}
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