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Split RegisterClass 'Methods' into MethodProtos and MethodBodies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22929 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -257,14 +257,19 @@ def GR : RegisterClass<"IA64", i64, 64,
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r120, r121, r122, r123, r124, r125, r126, r127,
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r0, r1, r2, r12, r13, r15, r22]> // the last 15 are special (look down)
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{
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let Methods = [{
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iterator allocation_order_begin(MachineFunction &MF) const {
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let MethodProtos = [{
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iterator allocation_order_begin(MachineFunction &MF) const;
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GRClass::iterator
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GRClass::allocation_order_begin(MachineFunction &MF) const {
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// hide registers appropriately:
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return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
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}
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iterator allocation_order_end(MachineFunction &MF) const {
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GRClass::iterator
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GRClass::allocation_order_end(MachineFunction &MF) const {
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int numReservedRegs=7; // the 7 special registers r0,r1,r2,r12,r13 etc
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// we also can't allocate registers for use as locals if they're
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@ -20,11 +20,17 @@ def GPRC : RegisterClass<"PPC32", i32, 32,
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R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
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R16, R15, R14, R13, R31, R0, R1, LR]>
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{
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let Methods = [{
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iterator allocation_order_begin(MachineFunction &MF) const {
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let MethodProtos = [{
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iterator allocation_order_begin(MachineFunction &MF) const;
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GPRCClass::iterator
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GPRCClass::allocation_order_begin(MachineFunction &MF) const {
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return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
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}
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iterator allocation_order_end(MachineFunction &MF) const {
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GPRCClass::iterator
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GPRCClass::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF))
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return end()-4;
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else
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@ -20,11 +20,17 @@ def GPRC : RegisterClass<"PPC64", i64, 64,
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R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
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R16, R15, R14, R13, R31, R0, R1, LR]>
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{
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let Methods = [{
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iterator allocation_order_begin(MachineFunction &MF) const {
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let MethodProtos = [{
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iterator allocation_order_begin(MachineFunction &MF) const;
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GPRCClass::iterator
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GPRCClass::allocation_order_begin(MachineFunction &MF) const {
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return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
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}
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iterator allocation_order_end(MachineFunction &MF) const {
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GPRCClass::iterator
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GPRCClass::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF))
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return end()-4;
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else
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@ -97,8 +97,13 @@ def IntRegs : RegisterClass<"V8", i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
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G0, // constant zero
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G5, G6, G7 // reserved for kernel
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]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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IntRegsClass::iterator
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IntRegsClass::allocation_order_end(MachineFunction &MF) const {
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// FIXME: These special regs should be taken out of the regclass!
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return end()-10; // Don't allocate special registers
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}
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}];
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@ -97,8 +97,13 @@ def IntRegs : RegisterClass<"V8", i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
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G0, // constant zero
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G5, G6, G7 // reserved for kernel
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]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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IntRegsClass::iterator
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IntRegsClass::allocation_order_end(MachineFunction &MF) const {
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// FIXME: These special regs should be taken out of the regclass!
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return end()-10; // Don't allocate special registers
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}
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}];
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@ -100,9 +100,11 @@ class RegisterClass<string namespace, ValueType regType, int alignment,
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//
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list<Register> MemberList = regList;
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// Methods - This member can be used to insert arbitrary code into a generated
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// register class. The normal usage of this is to overload virtual methods.
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code Methods = [{}];
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// MethodProtos/MethodBodies - These members can be used to insert arbitrary
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// code into a generated register class. The normal usage of this is to
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// overload virtual methods.
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code MethodProtos = [{}];
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code MethodBodies = [{}];
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}
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@ -75,8 +75,12 @@ let Namespace = "X86" in {
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def R8 : RegisterClass<"X86", i8, 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
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def R16 : RegisterClass<"X86", i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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R16Class::iterator
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R16Class::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate SP or BP
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else
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@ -86,8 +90,12 @@ def R16 : RegisterClass<"X86", i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
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}
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def R32 : RegisterClass<"X86", i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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R32Class::iterator
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R32Class::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate ESP or EBP
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else
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@ -115,8 +123,12 @@ def RFP : RegisterClass<"X86", f64, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
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// for transforming FPn allocations to STn registers)
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def RST : RegisterClass<"X86", f64, 32,
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[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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RSTClass::iterator
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RSTClass::allocation_order_end(MachineFunction &MF) const {
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return begin();
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}
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}];
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