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[mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2013-09-11 10:38:58 +00:00
parent 68831cbd41
commit ece929d623
3 changed files with 150 additions and 8 deletions
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12
lib/Target/Mips/MipsSEISelLowering.cpp
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@@ -160,6 +160,8 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
setOperationAction(ISD::STORE, Ty, Legal);
setOperationAction(ISD::ADD, Ty, Legal);
setOperationAction(ISD::SDIV, Ty, Legal);
setOperationAction(ISD::UDIV, Ty, Legal);
}
void MipsSETargetLowering::
@@ -877,6 +879,16 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
case Intrinsic::mips_bz_v:
return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
case Intrinsic::mips_div_s_b:
case Intrinsic::mips_div_s_h:
case Intrinsic::mips_div_s_w:
case Intrinsic::mips_div_s_d:
return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
case Intrinsic::mips_div_u_b:
case Intrinsic::mips_div_u_h:
case Intrinsic::mips_div_u_w:
case Intrinsic::mips_div_u_d:
return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
}
}