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https://github.com/c64scene-ar/llvm-6502.git
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[msan] Handling of atomic load/store, atomic rmw, cmpxchg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191287 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evgeniy Stepanov
parent
ae1fb8fc19
commit
ecf0fcd2b1
@ -66,6 +66,31 @@
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/// avoids storing origin to memory when a fully initialized value is stored.
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/// This way it avoids needless overwritting origin of the 4-byte region on
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/// a short (i.e. 1 byte) clean store, and it is also good for performance.
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///
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/// Atomic handling.
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///
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/// Ideally, every atomic store of application value should update the
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/// corresponding shadow location in an atomic way. Unfortunately, atomic store
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/// of two disjoint locations can not be done without severe slowdown.
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///
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/// Therefore, we implement an approximation that may err on the safe side.
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/// In this implementation, every atomically accessed location in the program
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/// may only change from (partially) uninitialized to fully initialized, but
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/// not the other way around. We load the shadow _after_ the application load,
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/// and we store the shadow _before_ the app store. Also, we always store clean
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/// shadow (if the application store is atomic). This way, if the store-load
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/// pair constitutes a happens-before arc, shadow store and load are correctly
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/// ordered such that the load will get either the value that was stored, or
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/// some later value (which is always clean).
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///
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/// This does not work very well with Compare-And-Swap (CAS) and
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/// Read-Modify-Write (RMW) operations. To follow the above logic, CAS and RMW
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/// must store the new shadow before the app operation, and load the shadow
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/// after the app operation. Computers don't work this way. Current
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/// implementation ignores the load aspect of CAS/RMW, always returning a clean
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/// value. It implements the store part as a simple atomic store by storing a
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/// clean shadow.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "msan"
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@ -487,7 +512,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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IRBuilder<> IRB(&I);
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Value *Val = I.getValueOperand();
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Value *Addr = I.getPointerOperand();
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Value *Shadow = getShadow(Val);
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Value *Shadow = I.isAtomic() ? getCleanShadow(Val) : getShadow(Val);
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Value *ShadowPtr = getShadowPtr(Addr, Shadow->getType(), IRB);
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StoreInst *NewSI =
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@ -498,6 +523,9 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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if (ClCheckAccessAddress)
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insertCheck(Addr, &I);
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if (I.isAtomic())
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I.setOrdering(addReleaseOrdering(I.getOrdering()));
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if (MS.TrackOrigins) {
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unsigned Alignment = std::max(kMinOriginAlignment, I.getAlignment());
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if (ClStoreCleanOrigin || isa<StructType>(Shadow->getType())) {
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@ -876,6 +904,38 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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ShadowOriginAndInsertPoint(Shadow, Origin, OrigIns));
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}
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AtomicOrdering addReleaseOrdering(AtomicOrdering a) {
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switch (a) {
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case NotAtomic:
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return NotAtomic;
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case Unordered:
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case Monotonic:
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case Release:
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return Release;
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case Acquire:
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case AcquireRelease:
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return AcquireRelease;
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case SequentiallyConsistent:
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return SequentiallyConsistent;
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}
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}
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AtomicOrdering addAcquireOrdering(AtomicOrdering a) {
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switch (a) {
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case NotAtomic:
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return NotAtomic;
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case Unordered:
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case Monotonic:
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case Acquire:
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return Acquire;
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case Release:
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case AcquireRelease:
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return AcquireRelease;
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case SequentiallyConsistent:
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return SequentiallyConsistent;
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}
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}
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// ------------------- Visitors.
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/// \brief Instrument LoadInst
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@ -884,7 +944,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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/// Optionally, checks that the load address is fully defined.
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void visitLoadInst(LoadInst &I) {
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assert(I.getType()->isSized() && "Load type must have size");
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IRBuilder<> IRB(&I);
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IRBuilder<> IRB(I.getNextNode());
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Type *ShadowTy = getShadowTy(&I);
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Value *Addr = I.getPointerOperand();
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if (LoadShadow) {
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@ -898,6 +958,9 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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if (ClCheckAccessAddress)
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insertCheck(I.getPointerOperand(), &I);
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if (I.isAtomic())
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I.setOrdering(addAcquireOrdering(I.getOrdering()));
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if (MS.TrackOrigins) {
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if (LoadShadow) {
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unsigned Alignment = std::max(kMinOriginAlignment, I.getAlignment());
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@ -917,6 +980,37 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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StoreList.push_back(&I);
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}
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void handleCASOrRMW(Instruction &I) {
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assert(isa<AtomicRMWInst>(I) || isa<AtomicCmpXchgInst>(I));
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IRBuilder<> IRB(&I);
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Value *Addr = I.getOperand(0);
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Value *ShadowPtr = getShadowPtr(Addr, I.getType(), IRB);
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if (ClCheckAccessAddress)
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insertCheck(Addr, &I);
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// Only test the conditional argument of cmpxchg instruction.
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// The other argument can potentially be uninitialized, but we can not
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// detect this situation reliably without possible false positives.
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if (isa<AtomicCmpXchgInst>(I))
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insertCheck(I.getOperand(1), &I);
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IRB.CreateStore(getCleanShadow(&I), ShadowPtr);
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setShadow(&I, getCleanShadow(&I));
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}
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void visitAtomicRMWInst(AtomicRMWInst &I) {
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handleCASOrRMW(I);
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I.setOrdering(addReleaseOrdering(I.getOrdering()));
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}
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void visitAtomicCmpXchgInst(AtomicCmpXchgInst &I) {
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handleCASOrRMW(I);
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I.setOrdering(addReleaseOrdering(I.getOrdering()));
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}
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// Vector manipulation.
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void visitExtractElementInst(ExtractElementInst &I) {
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insertCheck(I.getOperand(1), &I);
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189
test/Instrumentation/MemorySanitizer/atomics.ll
Normal file
189
test/Instrumentation/MemorySanitizer/atomics.ll
Normal file
@ -0,0 +1,189 @@
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; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; atomicrmw xchg: store clean shadow, return clean shadow
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define i32 @AtomicRmwXchg(i32* %p, i32 %x) sanitize_memory {
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entry:
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%0 = atomicrmw xchg i32* %p, i32 %x seq_cst
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ret i32 %0
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}
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; CHECK: @AtomicRmwXchg
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; CHECK: store i32 0,
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; CHECK: atomicrmw xchg {{.*}} seq_cst
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; CHECK: store i32 0, {{.*}} @__msan_retval_tls
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; CHECK: ret i32
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; atomicrmw max: exactly the same as above
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define i32 @AtomicRmwMax(i32* %p, i32 %x) sanitize_memory {
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entry:
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%0 = atomicrmw max i32* %p, i32 %x seq_cst
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ret i32 %0
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}
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; CHECK: @AtomicRmwMax
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; CHECK: store i32 0,
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; CHECK: atomicrmw max {{.*}} seq_cst
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; CHECK: store i32 0, {{.*}} @__msan_retval_tls
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; CHECK: ret i32
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; cmpxchg: the same as above, but also check %a shadow
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define i32 @Cmpxchg(i32* %p, i32 %a, i32 %b) sanitize_memory {
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entry:
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%0 = cmpxchg i32* %p, i32 %a, i32 %b seq_cst
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ret i32 %0
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}
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; CHECK: @Cmpxchg
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; CHECK: store i32 0,
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; CHECK: icmp
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; CHECK: br
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; CHECK: @__msan_warning
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; CHECK: cmpxchg {{.*}} seq_cst
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; CHECK: store i32 0, {{.*}} @__msan_retval_tls
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; CHECK: ret i32
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; relaxed cmpxchg: bump up to "release"
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define i32 @CmpxchgMonotonic(i32* %p, i32 %a, i32 %b) sanitize_memory {
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entry:
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%0 = cmpxchg i32* %p, i32 %a, i32 %b monotonic
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ret i32 %0
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}
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; CHECK: @CmpxchgMonotonic
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; CHECK: store i32 0,
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; CHECK: icmp
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; CHECK: br
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; CHECK: @__msan_warning
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; CHECK: cmpxchg {{.*}} release
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; CHECK: store i32 0, {{.*}} @__msan_retval_tls
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; CHECK: ret i32
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; atomic load: preserve alignment, load shadow value after app value
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define i32 @AtomicLoad(i32* %p) sanitize_memory {
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entry:
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%0 = load atomic i32* %p seq_cst, align 16
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ret i32 %0
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}
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; CHECK: @AtomicLoad
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; CHECK: load atomic i32* {{.*}} seq_cst, align 16
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; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32* {{.*}}, align 16
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; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
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; CHECK: ret i32
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; atomic load: preserve alignment, load shadow value after app value
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define i32 @AtomicLoadAcquire(i32* %p) sanitize_memory {
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entry:
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%0 = load atomic i32* %p acquire, align 16
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ret i32 %0
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}
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; CHECK: @AtomicLoadAcquire
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; CHECK: load atomic i32* {{.*}} acquire, align 16
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; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32* {{.*}}, align 16
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; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
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; CHECK: ret i32
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; atomic load monotonic: bump up to load acquire
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define i32 @AtomicLoadMonotonic(i32* %p) sanitize_memory {
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entry:
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%0 = load atomic i32* %p monotonic, align 16
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ret i32 %0
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}
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; CHECK: @AtomicLoadMonotonic
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; CHECK: load atomic i32* {{.*}} acquire, align 16
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; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32* {{.*}}, align 16
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; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
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; CHECK: ret i32
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; atomic load unordered: bump up to load acquire
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define i32 @AtomicLoadUnordered(i32* %p) sanitize_memory {
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entry:
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%0 = load atomic i32* %p unordered, align 16
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ret i32 %0
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}
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; CHECK: @AtomicLoadUnordered
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; CHECK: load atomic i32* {{.*}} acquire, align 16
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; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32* {{.*}}, align 16
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; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
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; CHECK: ret i32
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; atomic store: preserve alignment, store clean shadow value before app value
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define void @AtomicStore(i32* %p, i32 %x) sanitize_memory {
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entry:
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store atomic i32 %x, i32* %p seq_cst, align 16
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ret void
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}
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; CHECK: @AtomicStore
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; CHECK-NOT: @__msan_param_tls
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; CHECK: store i32 0, i32* {{.*}}, align 16
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; CHECK: store atomic i32 %x, i32* %p seq_cst, align 16
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; CHECK: ret void
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; atomic store: preserve alignment, store clean shadow value before app value
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define void @AtomicStoreRelease(i32* %p, i32 %x) sanitize_memory {
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entry:
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store atomic i32 %x, i32* %p release, align 16
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ret void
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}
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; CHECK: @AtomicStoreRelease
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; CHECK-NOT: @__msan_param_tls
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; CHECK: store i32 0, i32* {{.*}}, align 16
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; CHECK: store atomic i32 %x, i32* %p release, align 16
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; CHECK: ret void
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; atomic store monotonic: bumped up to store release
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define void @AtomicStoreMonotonic(i32* %p, i32 %x) sanitize_memory {
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entry:
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store atomic i32 %x, i32* %p monotonic, align 16
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ret void
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}
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; CHECK: @AtomicStoreMonotonic
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; CHECK-NOT: @__msan_param_tls
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; CHECK: store i32 0, i32* {{.*}}, align 16
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; CHECK: store atomic i32 %x, i32* %p release, align 16
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; CHECK: ret void
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; atomic store unordered: bumped up to store release
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define void @AtomicStoreUnordered(i32* %p, i32 %x) sanitize_memory {
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entry:
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store atomic i32 %x, i32* %p unordered, align 16
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ret void
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}
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; CHECK: @AtomicStoreUnordered
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; CHECK-NOT: @__msan_param_tls
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; CHECK: store i32 0, i32* {{.*}}, align 16
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; CHECK: store atomic i32 %x, i32* %p release, align 16
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; CHECK: ret void
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@ -442,8 +442,8 @@ define i32 @ShadowLoadAlignmentLarge() nounwind uwtable sanitize_memory {
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}
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; CHECK: @ShadowLoadAlignmentLarge
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; CHECK: load i32* {{.*}} align 64
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; CHECK: load volatile i32* {{.*}} align 64
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; CHECK: load i32* {{.*}} align 64
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; CHECK: ret i32
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define i32 @ShadowLoadAlignmentSmall() nounwind uwtable sanitize_memory {
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@ -453,14 +453,14 @@ define i32 @ShadowLoadAlignmentSmall() nounwind uwtable sanitize_memory {
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}
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; CHECK: @ShadowLoadAlignmentSmall
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; CHECK: load i32* {{.*}} align 2
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; CHECK: load volatile i32* {{.*}} align 2
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; CHECK: load i32* {{.*}} align 2
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; CHECK: ret i32
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; CHECK-ORIGINS: @ShadowLoadAlignmentSmall
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; CHECK-ORIGINS: load volatile i32* {{.*}} align 2
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; CHECK-ORIGINS: load i32* {{.*}} align 2
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; CHECK-ORIGINS: load i32* {{.*}} align 4
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; CHECK-ORIGINS: load volatile i32* {{.*}} align 2
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; CHECK-ORIGINS: ret i32
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@ -600,8 +600,8 @@ define <8 x i8*> @VectorOfPointers(<8 x i8*>* %p) nounwind uwtable sanitize_memo
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}
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; CHECK: @VectorOfPointers
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; CHECK: load <8 x i64>*
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; CHECK: load <8 x i8*>*
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; CHECK: load <8 x i64>*
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; CHECK: store <8 x i64> {{.*}} @__msan_retval_tls
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; CHECK: ret <8 x i8*>
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