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R600/SI: Fix div_scale intrinsic.

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The operand that must match one of the others does matter,
and implement selecting for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211523 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-06-23 18:28:28 +00:00
parent d88f5b71c7
commit ed143b7c0c
6 changed files with 106 additions and 18 deletions
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28
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
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@@ -86,6 +86,7 @@ private:
bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
SDNode *SelectADD_SUB_I64(SDNode *N);
SDNode *SelectDIV_SCALE(SDNode *N);
// Include the pieces autogenerated from the target description.
#include "AMDGPUGenDAGISel.inc"
@@ -454,6 +455,9 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
PackedOffsetWidth);
}
case AMDGPUISD::DIV_SCALE: {
return SelectDIV_SCALE(N);
}
}
return SelectCode(N);
}
@@ -695,6 +699,30 @@ SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
}
SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
SDLoc SL(N);
EVT VT = N->getValueType(0);
assert(VT == MVT::f32 || VT == MVT::f64);
unsigned Opc
= (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
const SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
SDValue Ops[] = {
N->getOperand(0),
N->getOperand(1),
N->getOperand(2),
Zero,
Zero,
Zero,
Zero
};
return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
}
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
const AMDGPUTargetLowering& Lowering =
*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());