6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-27 00:21:03 +00:00
Code Issues Projects Releases Wiki Activity

Move base value of instruction to lookup table to prepare for case reduction.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29122 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey
2006-07-12 19:15:43 +00:00
parent 1bb3a40257
commit ed393433d2
1 changed files with 37 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
utils/TableGen/CodeEmitterGen.cpp
View File

@@ -77,21 +77,30 @@ void CodeEmitterGen::run(std::ostream &o) {
EmitSourceFileHeader("Machine Code Emitter", o); EmitSourceFileHeader("Machine Code Emitter", o);
std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::"; std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
std::vector<const CodeGenInstruction*> NumberedInstructions;
Target.getInstructionsByEnumValue(NumberedInstructions);
// Emit function declaration // Emit function declaration
o << "unsigned " << Target.getName() << "CodeEmitter::" o << "unsigned " << Target.getName() << "CodeEmitter::"
<< "getBinaryCodeForInstr(MachineInstr &MI) {\n" << "getBinaryCodeForInstr(MachineInstr &MI) {\n";
<< " unsigned Value = 0;\n"
<< " switch (MI.getOpcode()) {\n";
// Emit a case statement for each opcode // Emit instruction base values
for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end(); o << " static const unsigned InstBits[] = {\n";
I != E; ++I) { for (std::vector<const CodeGenInstruction*>::iterator
Record *R = *I; IN = NumberedInstructions.begin(),
if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue; EN = NumberedInstructions.end();
IN != EN; ++IN) {
const CodeGenInstruction *CGI = *IN;
Record *R = CGI->TheDef;
if (IN != NumberedInstructions.begin()) o << ",\n";
if (R->getName() == "PHI" || R->getName() == "INLINEASM") {
o << " 0U";
continue;
}
o << " case " << Namespace << R->getName() << ": {\n";
BitsInit *BI = R->getValueAsBitsInit("Inst"); BitsInit *BI = R->getValueAsBitsInit("Inst");
// For little-endian instruction bit encodings, reverse the bit order // For little-endian instruction bit encodings, reverse the bit order
@@ -119,20 +128,31 @@ void CodeEmitterGen::run(std::ostream &o) {
unsigned Value = 0; unsigned Value = 0;
const std::vector<RecordVal> &Vals = R->getValues(); const std::vector<RecordVal> &Vals = R->getValues();
DEBUG(o << " // prefilling: ");
// Start by filling in fixed values... // Start by filling in fixed values...
for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) { if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
Value |= B->getValue() << (e-i-1); Value |= B->getValue() << (e-i-1);
DEBUG(o << B->getValue());
} else {
DEBUG(o << "0");
} }
} }
DEBUG(o << "\n"); o << " " << Value << "U";
}
o << "\n };\n";
DEBUG(o << " // " << *R->getValue("Inst") << "\n"); // Emit initial function code
o << " Value = " << Value << "U;\n\n"; o << " const unsigned opcode = MI.getOpcode();\n"
<< " unsigned Value = InstBits[opcode];\n"
<< " switch (opcode) {\n";
// Emit a case statement for each opcode
for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
I != E; ++I) {
Record *R = *I;
if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
o << " case " << Namespace << R->getName() << ": {\n";
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector<RecordVal> &Vals = R->getValues();
// Loop over all of the fields in the instruction, determining which are the // Loop over all of the fields in the instruction, determining which are the
// operands to the instruction. // operands to the instruction.