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[arm-fast-isel] Doublewords only require word-alignment.
rdar://10528060 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1106,7 +1106,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
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case MVT::f32:
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if (!Subtarget->hasVFP2()) return false;
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StrOpc = ARM::VSTRS;
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// Unaligned stores need special handling.
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// Unaligned stores need special handling. Floats require word-alignment.
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if (Alignment && Alignment < 4) {
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unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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@ -1119,8 +1119,9 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
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break;
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case MVT::f64:
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if (!Subtarget->hasVFP2()) return false;
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// FIXME: Unaligned stores need special handling.
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if (Alignment && Alignment < 8) {
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// FIXME: Unaligned stores need special handling. Doublewords require
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// word-alignment.
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if (Alignment && Alignment < 4) {
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return false;
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}
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StrOpc = ARM::VSTRD;
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@ -180,3 +180,21 @@ entry:
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store float %add, float* %x1, align 1
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ret void
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}
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; Doublewords require only word-alignment.
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; rdar://10528060
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%struct.anon.0 = type { double }
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@foo_unpacked = common global %struct.anon.0 zeroinitializer, align 4
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define void @test5(double %a, double %b) nounwind {
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entry:
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; ARM: @test5
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; THUMB: @test5
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%add = fadd double %a, %b
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store double %add, double* getelementptr inbounds (%struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4
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; ARM: vstr d16, [r0]
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; THUMB: vstr d16, [r0]
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ret void
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}
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