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[Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225270 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -3442,7 +3442,7 @@ defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
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// if ([!]Pv[.new]) mem[bhwd](##global)=Rt
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// if ([!]Pv[.new]) mem[bhwd](##global)=Rt
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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let Uses = [GP], validSubTargets = HasV4SubT in
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let validSubTargets = HasV4SubT in
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class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
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class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
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Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
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: T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
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: T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
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@@ -3452,7 +3452,7 @@ class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
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let BaseOpcode = BaseOp#_abs;
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let BaseOpcode = BaseOp#_abs;
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}
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}
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let Uses = [GP], validSubTargets = HasV4SubT in
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let validSubTargets = HasV4SubT in
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multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
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multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
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bits<2> MajOp, bit isHalf = 0> {
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bits<2> MajOp, bit isHalf = 0> {
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// Set BaseOpcode same as absolute addressing instructions so that
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// Set BaseOpcode same as absolute addressing instructions so that
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