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Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom

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part was always forced to be sextload, even when we needed an zextload.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-10-07 00:58:36 +00:00
parent 0c79fed5f9
commit ed83a7019b
1 changed files with 2 additions and 3 deletions
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5
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -4474,13 +4474,12 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
SDOperand Chain = Node->getOperand(0);
SDOperand Ptr = Node->getOperand(1);
MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
unsigned LType = Node->getConstantOperandVal(4);
ISD::LoadExtType LType = (ISD::LoadExtType)Node->getConstantOperandVal(4);
if (EVT == NVT)
Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
else
Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
EVT);
Lo = DAG.getExtLoad(LType, NVT, Chain, Ptr, Node->getOperand(2), EVT);
// Remember that we legalized the chain.
AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));