mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-29 10:32:47 +00:00
- Clean up formal argument lowering code. Prepare for vector pass by value work.
- Fixed vararg support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27985 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
634c76c08c
commit
eda65fa20b
@ -366,12 +366,14 @@ X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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std::vector<SDOperand> Args = TargetLowering::LowerArguments(F, DAG);
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FormalArgs.clear();
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FormalArgLocs.clear();
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// This sets BytesToPopOnReturn, BytesCallerReserves, etc. which have to be set
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// before the rest of the function can be lowered.
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if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
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PreprocessFastCCArguments(Args[0], F, DAG);
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PreprocessFastCCArguments(Args, F, DAG);
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else
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PreprocessCCCArguments(Args[0], F, DAG);
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PreprocessCCCArguments(Args, F, DAG);
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return Args;
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}
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@ -400,28 +402,74 @@ X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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// C Calling Convention implementation
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//===----------------------------------------------------------------------===//
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void X86TargetLowering::PreprocessCCCArguments(SDOperand Op, Function &F,
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SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues();
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static unsigned getFormalArgSize(MVT::ValueType ObjectVT) {
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unsigned ObjSize = 0;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8: ObjSize = 1; break;
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case MVT::i16: ObjSize = 2; break;
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case MVT::i32: ObjSize = 4; break;
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case MVT::i64: ObjSize = 8; break;
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case MVT::f32: ObjSize = 4; break;
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case MVT::f64: ObjSize = 8; break;
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}
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return ObjSize;
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}
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static std::vector<SDOperand> getFormalArgObjects(SDOperand Op) {
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unsigned Opc = Op.getOpcode();
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std::vector<SDOperand> Objs;
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if (Opc == ISD::TRUNCATE) {
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Op = Op.getOperand(0);
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assert(Op.getOpcode() == ISD::AssertSext ||
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Op.getOpcode() == ISD::AssertZext);
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Objs.push_back(Op.getOperand(0));
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} else if (Opc == ISD::FP_ROUND) {
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Objs.push_back(Op.getOperand(0));
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} else if (Opc == ISD::BUILD_PAIR) {
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Objs.push_back(Op.getOperand(0));
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Objs.push_back(Op.getOperand(1));
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} else {
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Objs.push_back(Op);
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}
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return Objs;
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}
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void X86TargetLowering::PreprocessCCCArguments(std::vector<SDOperand>Args,
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Function &F, SelectionDAG &DAG) {
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unsigned NumArgs = Args.size();
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Add DAG nodes to load the arguments... On entry to a function on the X86,
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// the stack frame looks like this:
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//
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// [ESP] -- return address
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// [ESP + 4] -- first argument (leftmost lexically)
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// [ESP + 8] -- second argument, if first argument is four bytes in size
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// ...
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//
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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for (unsigned i = 0; i < NumArgs; ++i) {
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MVT::ValueType ObjectVT = Op.Val->getValueType(i);
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unsigned ArgIncrement = 4;
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unsigned ObjSize;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8: ObjSize = 1; break;
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case MVT::i16: ObjSize = 2; break;
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case MVT::i32: ObjSize = 4; break;
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case MVT::i64: ObjSize = ArgIncrement = 8; break;
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case MVT::f32: ObjSize = 4; break;
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case MVT::f64: ObjSize = ArgIncrement = 8; break;
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SDOperand Op = Args[i];
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std::vector<SDOperand> Objs = getFormalArgObjects(Op);
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for (std::vector<SDOperand>::iterator I = Objs.begin(), E = Objs.end();
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I != E; ++I) {
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SDOperand Obj = *I;
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MVT::ValueType ObjectVT = Obj.getValueType();
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unsigned ArgIncrement = 4;
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unsigned ObjSize = getFormalArgSize(ObjectVT);
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if (ObjSize == 8)
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ArgIncrement = 8;
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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std::pair<FALocInfo, FALocInfo> Loc =
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std::make_pair(FALocInfo(FALocInfo::StackFrameLoc, FI), FALocInfo());
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FormalArgLocs.push_back(Loc);
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ArgOffset += ArgIncrement; // Move on to the next argument...
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}
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ArgOffset += ArgIncrement; // Move on to the next argument...
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}
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// If the function takes variable number of arguments, make a frame index for
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@ -438,39 +486,13 @@ void X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Add DAG nodes to load the arguments... On entry to a function on the X86,
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// the stack frame looks like this:
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//
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// [ESP] -- return address
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// [ESP + 4] -- first argument (leftmost lexically)
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// [ESP + 8] -- second argument, if first argument is four bytes in size
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// ...
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//
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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for (unsigned i = 0; i < NumArgs; ++i) {
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MVT::ValueType ObjectVT = Op.Val->getValueType(i);
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unsigned ArgIncrement = 4;
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unsigned ObjSize;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8: ObjSize = 1; break;
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case MVT::i16: ObjSize = 2; break;
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case MVT::i32: ObjSize = 4; break;
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case MVT::i64: ObjSize = ArgIncrement = 8; break;
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case MVT::f32: ObjSize = 4; break;
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case MVT::f64: ObjSize = ArgIncrement = 8; break;
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}
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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// Create the SelectionDAG nodes corresponding to a load from this parameter
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unsigned FI = FormalArgLocs[i].first.Loc;
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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SDOperand ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
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DAG.getSrcValue(NULL));
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SDOperand ArgValue = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(),
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FIN, DAG.getSrcValue(NULL));
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FormalArgs.push_back(ArgValue);
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ArgOffset += ArgIncrement; // Move on to the next argument...
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}
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}
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@ -715,13 +737,64 @@ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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static unsigned FASTCC_NUM_INT_ARGS_INREGS = 0;
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static void
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DetermineFastCCFormalArgSizeNumRegs(MVT::ValueType ObjectVT,
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unsigned &ObjSize, unsigned &NumIntRegs) {
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ObjSize = 0;
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NumIntRegs = 0;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
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NumIntRegs = 1;
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else
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ObjSize = 1;
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break;
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case MVT::i16:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
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NumIntRegs = 1;
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else
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ObjSize = 2;
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break;
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case MVT::i32:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
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NumIntRegs = 1;
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else
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ObjSize = 4;
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break;
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case MVT::i64:
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if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
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NumIntRegs = 2;
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} else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
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NumIntRegs = 1;
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ObjSize = 4;
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} else
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ObjSize = 8;
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case MVT::f32:
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ObjSize = 4;
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break;
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case MVT::f64:
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ObjSize = 8;
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break;
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}
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}
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void
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X86TargetLowering::PreprocessFastCCArguments(SDOperand Op, Function &F,
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SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues();
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X86TargetLowering::PreprocessFastCCArguments(std::vector<SDOperand>Args,
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Function &F, SelectionDAG &DAG) {
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unsigned NumArgs = Args.size();
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Add DAG nodes to load the arguments... On entry to a function the stack
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// frame looks like this:
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//
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// [ESP] -- return address
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// [ESP + 4] -- first nonreg argument (leftmost lexically)
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// [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
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// ...
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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// Keep track of the number of integer regs passed so far. This can be either
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@ -730,53 +803,77 @@ X86TargetLowering::PreprocessFastCCArguments(SDOperand Op, Function &F,
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unsigned NumIntRegs = 0;
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for (unsigned i = 0; i < NumArgs; ++i) {
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MVT::ValueType ObjectVT = Op.Val->getValueType(i);
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unsigned ArgIncrement = 4;
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unsigned ObjSize = 0;
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SDOperand ArgValue;
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SDOperand Op = Args[i];
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std::vector<SDOperand> Objs = getFormalArgObjects(Op);
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for (std::vector<SDOperand>::iterator I = Objs.begin(), E = Objs.end();
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I != E; ++I) {
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SDOperand Obj = *I;
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MVT::ValueType ObjectVT = Obj.getValueType();
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unsigned ArgIncrement = 4;
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unsigned ObjSize = 0;
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unsigned NumRegs = 0;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
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++NumIntRegs;
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break;
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DetermineFastCCFormalArgSizeNumRegs(ObjectVT, ObjSize, NumRegs);
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if (ObjSize == 8)
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ArgIncrement = 8;
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unsigned Reg;
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std::pair<FALocInfo,FALocInfo> Loc = std::make_pair(FALocInfo(),
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FALocInfo());
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if (NumRegs) {
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
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X86::R8RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = MVT::i8;
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break;
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case MVT::i16:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
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X86::R16RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = MVT::i16;
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break;
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case MVT::i32:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
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X86::R32RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = MVT::i32;
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break;
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case MVT::i64:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
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X86::R32RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = MVT::i32;
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if (NumRegs == 2) {
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Reg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
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Loc.second.Kind = FALocInfo::LiveInRegLoc;
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Loc.second.Loc = Reg;
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Loc.second.Typ = MVT::i32;
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}
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break;
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}
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}
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if (ObjSize) {
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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if (ObjectVT == MVT::i64 && NumRegs) {
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Loc.second.Kind = FALocInfo::StackFrameLoc;
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Loc.second.Loc = FI;
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} else {
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Loc.first.Kind = FALocInfo::StackFrameLoc;
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Loc.first.Loc = FI;
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}
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ArgOffset += ArgIncrement; // Move on to the next argument.
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}
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ObjSize = 1;
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break;
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case MVT::i16:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
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++NumIntRegs;
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break;
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}
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ObjSize = 2;
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break;
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case MVT::i32:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
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++NumIntRegs;
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break;
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}
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ObjSize = 4;
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break;
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case MVT::i64:
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if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
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NumIntRegs += 2;
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break;
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} else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
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ArgOffset += 4;
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NumIntRegs = FASTCC_NUM_INT_ARGS_INREGS;
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break;
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}
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ObjSize = ArgIncrement = 8;
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break;
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case MVT::f32: ObjSize = 4; break;
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case MVT::f64: ObjSize = ArgIncrement = 8; break;
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FormalArgLocs.push_back(Loc);
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}
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if (ObjSize)
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ArgOffset += ArgIncrement; // Move on to the next argument.
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}
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// Make sure the instruction takes 8n+4 bytes to make sure the start of the
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@ -815,131 +912,35 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Add DAG nodes to load the arguments... On entry to a function the stack
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// frame looks like this:
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//
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// [ESP] -- return address
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// [ESP + 4] -- first nonreg argument (leftmost lexically)
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// [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
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// ...
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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// Keep track of the number of integer regs passed so far. This can be either
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// 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
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// used).
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unsigned NumIntRegs = 0;
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for (unsigned i = 0; i < NumArgs; ++i) {
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MVT::ValueType ObjectVT = Op.Val->getValueType(i);
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unsigned ArgIncrement = 4;
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unsigned ObjSize = 0;
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MVT::ValueType VT = Op.Val->getValueType(i);
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std::pair<FALocInfo, FALocInfo> Loc = FormalArgLocs[i];
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SDOperand ArgValue;
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bool hasUse = !Op.Val->hasNUsesOfValue(0, i);
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
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if (hasUse) {
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unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
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X86::R8RegisterClass);
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ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
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DAG.setRoot(ArgValue.getValue(1));
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if (ObjectVT == MVT::i1)
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// FIXME: Should insert a assertzext here.
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ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
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}
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++NumIntRegs;
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break;
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}
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ObjSize = 1;
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break;
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case MVT::i16:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
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if (hasUse) {
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unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
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X86::R16RegisterClass);
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ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
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DAG.setRoot(ArgValue.getValue(1));
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}
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++NumIntRegs;
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break;
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}
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ObjSize = 2;
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break;
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case MVT::i32:
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if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) {
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if (hasUse) {
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unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
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X86::R32RegisterClass);
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ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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DAG.setRoot(ArgValue.getValue(1));
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}
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++NumIntRegs;
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break;
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}
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ObjSize = 4;
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break;
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case MVT::i64:
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if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
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if (hasUse) {
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unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
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unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
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SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
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SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
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DAG.setRoot(Hi.getValue(1));
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||||
|
||||
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
|
||||
}
|
||||
NumIntRegs += 2;
|
||||
break;
|
||||
} else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
|
||||
if (hasUse) {
|
||||
unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
|
||||
SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
|
||||
DAG.setRoot(Low.getValue(1));
|
||||
|
||||
// Load the high part from memory.
|
||||
// Create the frame index object for this incoming parameter...
|
||||
int FI = MFI->CreateFixedObject(4, ArgOffset);
|
||||
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
|
||||
SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
|
||||
DAG.getSrcValue(NULL));
|
||||
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
|
||||
}
|
||||
ArgOffset += 4;
|
||||
NumIntRegs = FASTCC_NUM_INT_ARGS_INREGS;
|
||||
break;
|
||||
}
|
||||
ObjSize = ArgIncrement = 8;
|
||||
break;
|
||||
case MVT::f32: ObjSize = 4; break;
|
||||
case MVT::f64: ObjSize = ArgIncrement = 8; break;
|
||||
if (Loc.first.Kind == FALocInfo::StackFrameLoc) {
|
||||
// Create the SelectionDAG nodes corresponding to a load from this parameter
|
||||
SDOperand FIN = DAG.getFrameIndex(Loc.first.Loc, MVT::i32);
|
||||
ArgValue = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(), FIN,
|
||||
DAG.getSrcValue(NULL));
|
||||
} else {
|
||||
// Must be a CopyFromReg
|
||||
ArgValue= DAG.getCopyFromReg(DAG.getRoot(), Loc.first.Loc, Loc.first.Typ);
|
||||
}
|
||||
|
||||
if (ObjSize) {
|
||||
// Create the frame index object for this incoming parameter...
|
||||
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
|
||||
|
||||
// Create the SelectionDAG nodes corresponding to a load from this
|
||||
// parameter.
|
||||
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
|
||||
|
||||
ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
|
||||
DAG.getSrcValue(NULL));
|
||||
} else if (ArgValue.Val == 0) {
|
||||
if (MVT::isInteger(ObjectVT))
|
||||
ArgValue = DAG.getConstant(0, ObjectVT);
|
||||
else
|
||||
ArgValue = DAG.getConstantFP(0, ObjectVT);
|
||||
if (Loc.second.Kind != FALocInfo::None) {
|
||||
SDOperand ArgValue2;
|
||||
if (Loc.second.Kind == FALocInfo::StackFrameLoc) {
|
||||
// Create the SelectionDAG nodes corresponding to a load from this parameter
|
||||
SDOperand FIN = DAG.getFrameIndex(Loc.second.Loc, MVT::i32);
|
||||
ArgValue2 = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(), FIN,
|
||||
DAG.getSrcValue(NULL));
|
||||
} else {
|
||||
// Must be a CopyFromReg
|
||||
ArgValue2 = DAG.getCopyFromReg(DAG.getRoot(),
|
||||
Loc.second.Loc, Loc.second.Typ);
|
||||
}
|
||||
ArgValue = DAG.getNode(ISD::BUILD_PAIR, VT, ArgValue, ArgValue2);
|
||||
}
|
||||
FormalArgs.push_back(ArgValue);
|
||||
|
||||
if (ObjSize)
|
||||
ArgOffset += ArgIncrement; // Move on to the next argument.
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -349,8 +349,28 @@ namespace llvm {
|
||||
/// Formal arguments lowered to load and CopyFromReg ops.
|
||||
std::vector<SDOperand> FormalArgs;
|
||||
|
||||
/// Formal arguments locations (frame indices and registers).
|
||||
struct FALocInfo {
|
||||
enum FALocKind {
|
||||
None,
|
||||
StackFrameLoc,
|
||||
LiveInRegLoc,
|
||||
} Kind;
|
||||
|
||||
int Loc;
|
||||
MVT::ValueType Typ;
|
||||
|
||||
FALocInfo() : Kind(None), Loc(0), Typ(MVT::isVoid) {};
|
||||
FALocInfo(enum FALocKind k, int fi) : Kind(k), Loc(fi), Typ(MVT::isVoid) {};
|
||||
FALocInfo(enum FALocKind k, int r, MVT::ValueType vt)
|
||||
: Kind(k), Loc(r), Typ(vt) {};
|
||||
};
|
||||
|
||||
std::vector<std::pair<FALocInfo, FALocInfo> > FormalArgLocs;
|
||||
|
||||
// C Calling Convention implementation.
|
||||
void PreprocessCCCArguments(SDOperand Op, Function &F, SelectionDAG &DAG);
|
||||
void PreprocessCCCArguments(std::vector<SDOperand>Args, Function &F,
|
||||
SelectionDAG &DAG);
|
||||
void LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
|
||||
std::pair<SDOperand, SDOperand>
|
||||
LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
|
||||
@ -359,7 +379,8 @@ namespace llvm {
|
||||
|
||||
// Fast Calling Convention implementation.
|
||||
void
|
||||
PreprocessFastCCArguments(SDOperand Op, Function &F, SelectionDAG &DAG);
|
||||
PreprocessFastCCArguments(std::vector<SDOperand>Args, Function &F,
|
||||
SelectionDAG &DAG);
|
||||
void
|
||||
LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
|
||||
std::pair<SDOperand, SDOperand>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user