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big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not

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the lo-reg first.  This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34983 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-03-06 20:01:06 +00:00
parent 622adea47f
commit edf2e8da25
1 changed files with 5 additions and 0 deletions
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5
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -1675,6 +1675,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
if (Tmp2.getValueType() != MVT::Vector) { if (Tmp2.getValueType() != MVT::Vector) {
SDOperand Lo, Hi; SDOperand Lo, Hi;
ExpandOp(Tmp2, Lo, Hi); ExpandOp(Tmp2, Lo, Hi);
// Big endian systems want the hi reg first.
if (!TLI.isLittleEndian())
std::swap(Lo, Hi);
if (Hi.Val) if (Hi.Val)
Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
else else