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Properly constrain register classes for sub-registers.

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Not all GR64 registers have sub_8bit sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157150 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-05-20 06:38:37 +00:00
parent 8e86929e3c
commit ee0d5d4398
2 changed files with 4 additions and 2 deletions
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2
lib/CodeGen/SelectionDAG/FastISel.cpp
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@ -1345,6 +1345,8 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
"Cannot yet extract from physregs");
const TargetRegisterClass *RC = MRI.getRegClass(Op0);
MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
DL, TII.get(TargetOpcode::COPY), ResultReg)
.addReg(Op0, getKillRegState(Op0IsKill), Idx);

4
test/CodeGen/X86/fast-isel.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 -mattr=sse2
; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10
; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2
; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10
; This tests very minimal fast-isel functionality.