From ee27f57a6a4dd7fa9259b3604f563907da1f65ef Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 11 Apr 2005 20:08:52 +0000
Subject: [PATCH] Fix expansion of shifts by exactly NVT bits on arch's (like
 X86) that have masking shifts.

This fixes the miscompilation of this:

long long test1(unsigned A, unsigned B) {
        return ((unsigned long long)A << 32) | B;
}

into this:

test1:
        movl 4(%esp), %edx
        movl %edx, %eax
        orl 8(%esp), %eax
        ret

allowing us to generate this instead:

test1:
        movl 4(%esp), %edx
        movl 8(%esp), %eax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21230 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index e1d9836f812..e4213171724 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1500,6 +1500,9 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
       } else if (Cst > NVTBits) {
         Lo = DAG.getConstant(0, NVT);
         Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
+      } else if (Cst == NVTBits) {
+        Lo = DAG.getConstant(0, NVT);
+        Hi = InL;
       } else {
         Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
         Hi = DAG.getNode(ISD::OR, NVT,
@@ -1514,6 +1517,9 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
       } else if (Cst > NVTBits) {
         Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
         Hi = DAG.getConstant(0, NVT);
+      } else if (Cst == NVTBits) {
+        Lo = InH;
+        Hi = DAG.getConstant(0, NVT);
       } else {
         Lo = DAG.getNode(ISD::OR, NVT,
            DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
@@ -1530,6 +1536,10 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
                            DAG.getConstant(Cst-NVTBits, ShTy));
         Hi = DAG.getNode(ISD::SRA, NVT, InH, 
                               DAG.getConstant(NVTBits-1, ShTy));
+      } else if (Cst == NVTBits) {
+        Lo = InH;
+        Hi = DAG.getNode(ISD::SRA, NVT, InH, 
+                              DAG.getConstant(NVTBits-1, ShTy));
       } else {
         Lo = DAG.getNode(ISD::OR, NVT,
            DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),