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implement MULHU/MULHS for 64-bit multiplies

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-12-17 22:30:00 +00:00
parent 37949f5c2b
commit ee3d5fba54
2 changed files with 22 additions and 0 deletions
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11
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -278,6 +278,17 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: break; default: break;
case ISD::MULHU:
case ISD::MULHS: {
SDOperand MulLHS = Select(N->getOperand(0));
SDOperand MulRHS = Select(N->getOperand(1));
unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
}
case ISD::RET: { case ISD::RET: {
if (N->getNumOperands() == 2) { if (N->getNumOperands() == 2) {
SDOperand Chain = Select(N->getOperand(0)); // Token chain. SDOperand Chain = Select(N->getOperand(0)); // Token chain.

11
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -278,6 +278,17 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: break; default: break;
case ISD::MULHU:
case ISD::MULHS: {
SDOperand MulLHS = Select(N->getOperand(0));
SDOperand MulRHS = Select(N->getOperand(1));
unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
}
case ISD::RET: { case ISD::RET: {
if (N->getNumOperands() == 2) { if (N->getNumOperands() == 2) {
SDOperand Chain = Select(N->getOperand(0)); // Token chain. SDOperand Chain = Select(N->getOperand(0)); // Token chain.